Webinar: Getting Ahead with the Antenna Array Design and Simulation (CST) - Feb 25, 2016

 
Event status: Not started ( Register NOW)
Date and time: Thursday, February 25, 2016 11:00 am
Eastern Standard Time (New York, GMT-05:00)
Change time zone
  Thursday, February 25, 2016 8:00 am
Pacific Standard Time (San Francisco, GMT-08:00)
  Thursday, February 25, 2016 11:00 am
Eastern Standard Time (New York, GMT-05:00)
  Thursday, February 25, 2016 9:30 pm
India Time (Mumbai, GMT+05:30)
Program:
Getting Ahead with... 2016 Webinars
Panelist(s) Info:
Arnab Bhattacharya received his M.Sc. degrees in Electrical Engineering from Karlsruhe Institute of Technology, Germany and Universite catholique de Louvain, Belgium. He joined CST in 2012 as an Application Engineer where his main area of work involves high frequency applications and EMC/EMI simulation.
Duration: 1 hour
Description:
An antenna array allows us to achieve high gain with multiple radiating elements and a phased array in addition offers the possibility to shape and steer the beam without changing the array geometry. Traditionally such arrays have been used in defense applications, particularly for radar, but this is changing as we see increased commercial use, especially with the advent of on-the-move access to high bandwidth data. The challenge lies in achieving these radiating characteristics while keeping the undesired effects such as the mutual coupling between the elements due to their proximity to each other at a minimum. The design of these large arrays is typically achieved in two steps where first the element design is obtained by optimizing the Active Element Impedance and Active Element Pattern over all frequencies and scan angles and in the second step the array design is validated by inspecting the real scanning behavior and including the non-periodic structure effects. Each of these stages call for appropriate solver technologies to complete the design efficiently in the least amount of time. During this webinar we will look at the new array design functionality which makes the design of phased arrays, at both the cell and full array level substantially more efficient and powerful.
 



Review Article Be the first to review this article
SI2

AMIQ: dvteclipse

Featured Video
Editorial
Peggy AycinenaIP Showcase
by Peggy Aycinena
Grant Pierce: Grand Challenges in IP
More Editorial  
Jobs
LVS for PDK Design Engineer SILICON VALLEY for EDA Careers at San Jose, CA
LVS PEX DESIGN ENGINEERS SILICON VALLEY for EDA Careers at San Jose, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Upcoming Events
EMC PCB Design Integration at 13727 460 Ct SE North Bend WA - Jun 6 - 9, 2017
DAC 2017 Conference at Austin TX - Jun 18 - 22, 2017
2017 FLEX Conference at Monterey Conference Center 1 Portola Plaza, Monterey CA - Jun 19 - 22, 2017
MPSoc Forum 2017 - July 2 - 7, 2017, Les Tresoms Hotel, Annecy, France at Les Tresoms Hotel Annecy France - Jul 2 - 7, 2017
NEC: CyberWorkbench
Verific: SystemVerilog & VHDL Parsers
DownStream: Solutions for Post Processing PCB Designs
DAC2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy