Highlights:SAN JOSE, Calif., Jan. 11, 2016 — (PRNewswire) — Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its customers have completed more than 200 tapeouts using the Tempus™ Timing Signoff Solution. Since its introduction in the fall of 2013, nearly 100 customers have rapidly deployed the solution on a wide range of production designs, from mixed-signal chips to high-speed processor cores to large 100M+-instance systems on chip (SoCs), across mature process nodes and advanced FinFET nodes. Customers have significantly benefited from the 5-10X faster signoff timing closure and significant power, performance and area (PPA) gains.
The Cadence® Tempus Timing Signoff Solution includes massively parallelized computation and physically aware timing optimization capabilities that enable designers to reduce time to signoff closure by significantly reducing engineering change order (ECO) iterations by an order of magnitude. Using the multi-threaded and distributable path-based analysis (PBA) capability, customers can also analyze thousands of critical paths in their design in a matter of minutes while eliminating hundreds of pessimistic violations reported otherwise by traditional static timing-analysis methods. The tool's unique physically aware surgical timing optimization enables significant PPA gains in addition to any gains achieved using design implementation tools. Finally, customers have realized full-chip signoff accuracy within 1.5 percent of SPICE through multiple foundry certifications and qualifications.
"The Tempus Timing Signoff Solution is the most rapidly adopted signoff tool in Cadence history, and our customers have reached production use in a wide variety of applications, including Internet of Things (IoT), communications, computing, integrated radio frequency (RF) and mixed-signal ICs," said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. "Customers using the Tempus Timing Signoff Solution have observed significant productivity gains, achieving faster runtimes and reductions in ECO loops so they can get their designs to market faster."
The Tempus Timing Signoff Solution is a silicon-accurate, color-aware timing signoff and signal integrity analysis tool that supports advanced-node design requirements for waveform propagation, Miller Effect, ultra-low power, and variation associated with multi-patterning technologies. For more information on the Tempus Timing Signoff Solution, please visit www.cadence.com/news/tempus.
"The Tempus Timing Signoff Solution has been our timing tool for all of our SoCs that enable smart TV, set-top boxes and media connectivity. Its runtime performance, coupled with integration within the Cadence Innovus™ Implementation System, has allowed us to significantly reduce the time we spend in timing signoff and, ultimately, time to market."
- Jacques Martinella, vice president, engineering at Sigma Designs
"The size and complexity characteristics of our latest design required a timing solution that could handle more than 50M cells quickly and efficiently. We determined that the Tempus Timing Signoff Solution was the right timing platform to address our signoff analysis and closure needs. With strong support from Cadence, we expect continued success in taping out complex designs at 28nm and beyond."
- Toru Hiyama, general manager for Platform Advanced Engineering Operation, Information and Telecommunication System Company, Hitachi, Ltd.
"The Tempus Timing Signoff Solution has enabled us to complete several successful tapeouts of our datacenter interconnect solutions. We were able to effectively use the tool for distributed multi-mode, multi-corner (MMMC) timing analysis and closure to get our products out the door and into the fab to meet our customers' aggressive schedules."
- Lawrence Tse, vice president of engineering at Inphi
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.
© 2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks and Innovus and Tempus are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.
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SOURCE Cadence Design Systems, Inc.
|Cadence Design Systems, Inc.