Renesas Electronics Announces Development of an On-Chip SRAM to Enable Real-Time Image Processing Required in the Autonomous-Driving Cars Era

New SRAM Achieves Both a 688 Ps High-Speed Operation and a High Integration Density of 3.6 Mbit/mm² with 16nm Process

TOKYO — (BUSINESS WIRE) — December 10, 2015 — Renesas Electronics Corporation (TSE:6723), a premier supplier of advanced semiconductor solutions, today announced its successful development of a new dual-port on-chip static random access memory (SRAM) for in-vehicle infotainment system-on-chips (SoCs) in the 16 nanometer (nm) and later generations. The new SRAM is optimized for use as video buffer memory in automotive infotainment SoCs to realize the real-time image processing capabilities necessary for future autonomous-driving vehicle technologies. When testing the new SRAM in a state-of-the-art 16 nm process, it achieved both 688-picosecond (ps) high-speed operation under the low-voltage condition of 0.7 V and the industry-leading high level integration density of 3.6 Mbit/mm².

Recently, in-vehicle infotainment systems, such as car navigation systems and advanced driver assistance systems (ADAS), have achieved dramatic progress in preparation for the autonomous cars of the future. In these systems, real-time image processing technologies are critical for realizing autonomous-driving vehicles, and there are limits to improve this real-time processing capability by only increasing the integration density with even finer feature sizes and using higher clock frequencies.

To resolve these limitations, there have been efforts to improve performance further by using algorithms that break up images into smaller section and process those sections in parallel. The dual-ported on-chip SRAM is now desired for use with these algorithms, since it can perform write and read operations at the same time to achieve approximately twice the performance of standard single-ported on-chip SRAM. Compared to the single-ported SRAM, however, this dual-ported SRAM suffers from several problems, including not only requiring more chip area, but also increased power consumption when access speeds are increased, worse lower limit voltage margins, and other issues.

By adopting a dual-ported SRAM memory cell optimized for FinFET devices, Renesas has succeeded in resolving these issues. The company has also applied a word line boost type assist circuit technology developed for single-ported SRAM to enable high-speed read and write operations that are stable at lower voltages, and allow power consumption to be suppressed in a small chip area.

Key features of the new SRAM:

(1) Word line overdrive type assist circuit, which takes advantage of the features of the FinFET device, achieves low-voltage high-speed operation

Due to increasing variations in device elements associated with finer feature sizes in semiconductor processes, there has been a trend for device lower limit operating voltages to become worse. To resolve this issue, circuit technology ("assist circuits") that use circuit improvements was introduced. Previously, an optimization in which the word line voltage was lowered slightly at access time to assure stable operation during read operations.

This technique, however, had issues such as the operating margin during write being degraded and the read speed being reduced significantly. Renesas proposed for single-ported SRAM, and then adopted, the assist circuit method, which takes advantage of the FinFET device characteristics and, inversely compared to the early method, slightly increases the word line voltage and adjusts the pulse widths used during read and write operations. Then, Renesas has extended this assist circuit technology developed for single-ported SRAM and adopted it in the dual-ported SRAM for image processing. The results of test evaluation in a state-of-the-art 16 nm process were that Renesas verified stable, high-speed operation at 688 ps under the low-voltage condition of 0.7 V.

(2) Adoption of memory cell optimal for dual-ported SRAM, achieving the industry-leading integration density of 3.6 Mbit/mm²

Unlike single-ported SRAM, for dual-ported SRAM there are several different layout topologies for the bit cell. Although a planar MOSFET structure had been adopted up to now in processes through the 28 nm generation, Renesas has adopted a new FinFET device, which adopts a fin structure that suppresses process variations in the 16 nm process and clearly improves device characteristics. This new FinFET device has extremely strict layout restrictions, and it is difficult to use the layout structure that was optimal for earlier planar type devices. Also, a symmetrical layout structure is required to operate the devices stably, since MOS characteristics fluctuate wildly. In this new SRAM, Renesas has newly adopted a dual-port memory cell optimized for this FinFET device to have superlative symmetry and has optimized the design of the peripheral circuits as SRAM for real-time image processing. As a result, Renesas achieved a density of 3.6 Mbit/mm², an industry-leading high level of integration density. These results allow this technology to support the inclusion of even larger scales of on-chip SRAM, for which demand is increasing along with the demands for parallel processing.

Renesas’ newly-developed dual-ported SRAM for real-time image processing achieves both the speed and stable operation that were expected to be problematic as semiconductor fabrication processes move to even finer feature sizes, and furthermore suppresses power consumption and achieves reduced chip areas. The SRAM is expected to contribute significantly to improved real-time image processing performance in self-driving and leading-edge driver assistance systems of the future.

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