Researcher Sylvain Barraud Will Receive 2014 IEEE EDS Paul Rappaport Award For Work in Multi-Core/Shell-(SiGe/Si) Nanowire Transistors
GRENOBLE, France – Nov. 23, 2015 – CEA-Leti will present six invited papers at the 2015 IEEE International Electron Devices Meeting (IEDM) Dec. 7-9 in Washington, D.C., share the latest results in its new CoolCube program and host a workshop focusing on the Internet of Things on Dec. 6.
In addition, Leti research scientist Sylvain Barraud will receive the 2014 IEEE EDS Paul Rappaport Award for his work in multi-Core/Shell-(SiGe/Si) nanowire transistors. This award recognizes the best scientific paper targeting IEEE transactions on electron devices. The article was selected from more than 600 papers published in 2014.
On Dec. 8, Maud Vinet, Leti’s advanced CMOS manager, will present the latest on Leti’s CoolCube technique for stacking transistors sequentially in the same process flow for 3D-VLSI, at a panel discussion titled, “Is there a potential for a revolution in on-chip interconnect?”
Also on Dec. 8, Carlo Reita, director of nanoelectronics technical marketing and strategy, will participate in a panel discussion on “Emerging Devices – Will they solve the bottlenecks of CMOS?”
The Internet of Things workshop for invited guests at the Churchill Hotel will feature a keynote presentation on “Enabling Next-generation Innovation with 22FDX”, by Subramani Kengeri, vice president of GLOBALFOUNDRIES’ CMOS business unit. The workshop also will focus on energy challenges, new sensor capabilities and enabling applications:
- System challenges for IoT
- Ultra low-power CMOS
- Emerging embedded memories
- Ultra low-power global design
- Sensors for context awareness
- Energy scavenging
- Enabling medicine with IoT
Discussions, networking and cocktails will follow the presentations.
Subjects of the invited papers are:
- Issues for 200mm GaN/Si, from epitaxy to converter topologies
- Implementation of embedded neuromorphic circuits
- Large-area sensing surfaces
- Lensfree microscopy
- Technology scaling and reliability
- New challenges and opportunities for 3D integration
Leti researchers also will join partners to present four papers on vertical resistive RAM for neuromorphic applications, polysilicon nanowire NEMS, a 3D VLSI integration SiCO perspective on low k=4.5 spacer deposited at low temperature and a 3D computational study of van der Waals tunnel transistors.
About Leti (France)
As one of three advanced-research institutes within the CEA Technological Research Division, CEA Tech-Leti serves as a bridge between basic research and production of micro- and nanotechnologies that improve the lives of people around the world. It is committed to creating innovation and transferring it to industry. Backed by its portfolio of 2,800 patents, Leti partners with large industrials, SMEs and startups to tailor advanced solutions that strengthen their competitive positions. It has launched 54 startups. Its 8,500m² of new-generation cleanroom space feature 200mm and 300mm wafer processing of micro and nano solutions for applications ranging from space to smart devices. With a staff of more than 1,800, Leti is based in Grenoble, France, and has offices in Silicon Valley, Calif., and Tokyo. Follow us at www.leti.fr and @CEA_Leti.
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