Minimizing BoM cost and silicon area thanks to iLR-LaDiable capless regulator

Grenoble, France – November 16, 2015 - IoT and wearable devices have added to the challenge of reduction of BoM cost and silicon area that of changing the principles of voltage regulators to the point that their efficiency is no longer the major criteria.

Embedding features such as the Power Management Network (PMNet) in a SoC demands going further in the quest of performance: the new capless linear regulator  iLR-LaDiable reaches the operating zone to the best performances while preserving the stability.

Indeed, using a  Delta architecture without an external capacitor implies relying on the load capacitance instead: ensuring a correct matching is essential to avoid any load transient variation. In order to secure capless regulator implementation, Dolphin Integration includes in its specifications all the needed templates, profiles and abacus enabling sizing  the load capacitance for required load transient performances.

Macintosh HD:Users:cmv:Desktop:Communication:Annonces:iLR-LaDiable:Image Capless.png

Key features

  • Maximum Output current of 50 mA
  • 0.8 to 3.3 V programmable output voltage
  • Capless linear regulator (no off-chip capacitor needed)
  • Delivered with load transient template and abacus to ensure the proper matching between the regulator and its load
  • Complemented with an Over-voltage Protection Module (OPM) enabling to support a [1.9 V - 4.4 V] input voltage range for direct connection to a Li-Ion battery.

The iLR-LaDiable is the suitable regulator for supplying logic loads such as embedded memories and logic power Islands. To reach better optimizations of the overall SoC, Dolphin Integration offers a complete set of solutions, including  High Density Memories and Standard Cell Libraries.




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