SUNNYVALE, Calif. and MUNICH, Germany – Nov. 4, 2015 –
Real Intent, a provider of leading SoC and FPGA sign-off verification solutions
Will exhibit its Ascent and Meridian productsat the Design & Verification Conference & Exhibition Europe ( DVCon Europe) in Munich, Germany, next week through its European distribution partner EuropeLaunch. This two-day technical conference targets the application of standardized languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. Ascent products improve QoR and productivity of design teams by finding elusive bugs and getting rid of sources of uncertainty that are difficult to uncover using traditional Verilog or VHDL simulation. Meridian products accelerate sign-off verification of clock domain crossings and SDC in 500+M gate SoC designs.
Hosted by Accellera Systems Initiative, the second annual DVCon Europe is a very practical industry-focused conference on EDA standards and standardization. With a highly technical focus on System and IC design, verification and integration, DVCon Europe 2015 brings together industry experts, designers of electronic systems, ASICs and FPGAs, and those involved in the research, development and application of EDA tools and IP integration. It serves to boost the interest, use and development of EDA and IP standards in Europe. Real Intent exhibited its advanced SoC and FPGA sign-off verification solutions at the debut of DVCon Europe last year as well.
Foyer Großer Saal, Exhibit Table #E16
Prime exhibit times during coffee breaks, meals, and evening reception:
Wednesday, Nov. 11, 2015:
10:30 – 11:00, 12:30 – 13:30, 15:00 – 15:30, 18:00 – 20:00
Thursday, Nov. 12, 2015:
11:00 – 11:30, 12:30 – 14:00, 15:30 – 16:00
At the Holiday Inn Munich City Centre
81669 Munich, Germany
+49 (0) 89-4803-0
About Real Intent
Companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and advanced sign-off of electronic designs. Real Intent’s comprehensive CDC verification, advanced RTL analysis and sign-off solutions eliminate complex failure modes of SoCs, and lead the market in performance, capacity, accuracy and completeness. Please visit www.realintent.com for more information.
Real Intent and the Real Intent logo are registered trademarks, and Meridian, iDebug and Ascent are trademarks of Real Intent, Inc. All other trademarks and trade names are the property of their respective owners.
Clock Domain Crossing
EDA Electronic Design Automation
FPGA Field Programmable Gate Array
IP Intellectual Property
QoR Quality of Results
RTL Register Transfer Level
SDC Synopsys Design Constraints
SoC System on Chip
VHDL Very High-Level Design Language
Sarah Miller for Real Intent
ThinkBold Corporate Communications