Real Intent to Present Tutorial on Advanced Verification Solutions at ASICON China 2015

SUNNYVALE, CALIF. – Oct. 27, 2015 –   


Real Intent, a leading provider of SoC and FPGA sign-off verification solutions


Will present one of only six tutorials at the 11th International Conference on ASIC (ASICON 2015) in Chengdu, China, next week. Ramesh Dewangan, vice president of product strategy at Real Intent, will conduct a 90-minute tutorial session, “ New Challenges and Techniques for Clock Domain Crossing and Reset Sign-off.” His tutorial covers clock domain crossing (CDC) and reset signoff challenges due to the growing size and complexity of today’s SoCs and FPGAs. It spans issues related to clocks and resets, metastability and glitches for both RTL and physical implementation, as well as data correlation due to asynchronous clock convergence and divergence. 

The ASICON conference provides an international forum for VLSI circuit designers, ASIC users, system integrators, IC manufacturers and CAD/CAE tool developers to present their advancements and research. It gives academic and industry attendees the opportunity to network and exchange information. This three-day event features keynote speeches on state-of-the-art VLSI circuit, device, process design and manufacturing technologies, regular paper presentations, and tutorials delivered by leading experts in their respective fields. The conference also features an exhibition on EDA tools, foundry technologies, IC test facilities, and novel ASIC products.


Tutorial session T-5 presented by Ramesh Dewangan:

Tuesday, Nov. 3         10:15-12:15, Brunei Meeting Room, Wangjiang Club 2F 

At the Wanjiang Hotel

No.42 Xiashahepu Street, Chengdu, Sichuan, P.R.China

Tel: +86-28-84090658  Fax: +86-28-84791688

About Real Intent

Companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and advanced sign-off of electronic designs. Real Intent’s comprehensive CDC verification, advanced RTL analysis and sign-off solutions eliminate complex failure modes of SoCs, and lead the market in performance, capacity, accuracy and completeness. Please visit for more information.

Real Intent and the Real Intent logo are registered trademarks, and Meridian, iDebug and Ascent are trademarks of Real Intent, Inc. All other trademarks and trade names are the property of their respective owners.


CAD/CAE:           Computer-Aided Design/Computer-Aided Engineering
CDC:                    Clock Domain Crossing
EDA:                    Electronic Design Automation
IC                         Integrated Circuit
RTL:                     Register Transfer Level
SoC:                    Systems-on-Chip
VLSI:                    Very-Large-Scale Integration

Press contact:
Sarah Miller for Real Intent
ThinkBold Corporate Communications

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