DVCon Europe 2015 announces its Preliminary Technical Program Registration discount applies until October 1st, 2015

Sep 28, 2015 -- The Design and Verification Conference (DVCon) & Exhibition Europe is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative, DVCon Europe brings chip architects, design & verification engineers, and IP integrators the latest methodologies, techniques, applications and demonstrations for the practical use of EDA solutions for electronic design.

The conference will be held on Wednesday November 11th and Thursday November 12th, 2015 at the Holiday Inn Munich City Center, Hochstrasse 3, 81669 Munich, Germany.

Early bird registration discount is available through October 1st, 2015. Register today at: www.dvcon-europe.org/registration. Click here for Special hotel rates for attendees.

The Preliminary Technical Program is now available, covering the following themes:

  • System Level Design & Verification
  • Advanced Verification & Validation
  • Design for Functional Safety
  • IP Reuse and Design Automation
  • Analog and Mixed-Signal Design & Verification
  • Lower Power Techniques

DVCon Europe has selected high quality papers, tutorials and posters around best practices and user experiences on design and verification in SystemC, SystemVerilog, PSL, UVM, UPF, IP-XACT, and more.

The Highlights of DVCon Europe 2015 are:

  • Leading Industry Keynote Speaker: Hans Adlkofer, Vice President Automotive System Group, Infineon Technologies
  • 15 tutorials moderated by user companies, tool providers and training partners
  • Technical program covering 36 papers
  • Multiple tracks presenting 26 papers and a poster session hosting 10 posters
  • Exhibition show with demos from training partners, design tool and IP service providers
  • Gala Dinner included as part of the conference

ACCELLERA GLOBAL SPONSORS: ARM, Cadence, Intel, Mentor Graphics, Synopsys




Review Article Be the first to review this article
Aldec


Featured Video
Jobs
Salesforce Technical Lead   East Coast  for EDA Careers at Cherry Hill, New Jersey
Sr. Application Engineer for Mentor Graphics at Fremont, California
Senior Software Architect Internet for EDA Careers at San Jose, California
Hardware Engineer, Board Design for Arista Networks at Santa Clara, California
Senior Account Managers… FORMAL VERIFICATION...VALLEY for EDA Careers at San Jose, California
Upcoming Events
FLEX 2020 and MSTC 2020 at DoubleTree by Hilton 2050 Gateway Place San Jose CA - Feb 24 - 27, 2020
DVCon U.S. 2020 at DoubleTree Hotel San Jose CA - Mar 2 - 5, 2020
OFC 2020 - The Optical Networking and Communication Conference & Exhibition at San Diego Convention Center San Diego CA - Mar 8 - 12, 2020
DATE '2020 at ALPEXPO Grenoble France - Mar 9 - 13, 2020
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers



© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise