Cadence Receives Two TSMC Partner of the Year Awards for 10nm FinFET Solutions and Analog/Mixed-Signal IP

SAN JOSE, Calif., Sept. 28, 2015 — (PRNewswire) —  Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that it received two TSMC Partner of the Year awards at this year's TSMC Open Innovation Platform® (OIP) Ecosystem Forum. Cadence was presented with awards for both joint development of the 10nm FinFET design infrastructure and analog/mixed-signal IP.

Cadence Logo.

The award for joint development of the 10nm design infrastructure was given based on the early, in-depth collaboration between TSMC and Cadence on FinFET enablement and the development of this latest advanced-node technology for next-generation system-on-chip (SoC) designs. Cadence provides combined digital, signoff and custom/analog tool flows that are integrated on a common OpenAccess database, incorporating integrated signoff engines that have been validated by TSMC on high-performance reference designs. Cadence® tools certified for TSMC's 10nm process include Innovus™ Implementation System, Quantus™ QRC Extraction Solution, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution, Voltus-Fi Custom Power Integrity Solution, Virtuoso® custom IC advanced-node platform, Physical Verification System, Litho Electrical Analyzer and the entire Spectre® simulation platform. For more information on the Cadence tools, please visit www.cadence.com/products/Pages/all_products.aspx.

The analog/mixed-signal IP award was based on customer feedback, portfolio breadth, strong technical support capabilities and customer adoption/production volume. The Cadence IP portfolio is comprised of Denali® memory, interface, and analog IP and includes protocols such as DDR4, LPDDR4, ONFI 4, UFS, SATA, PCIe® 4.0, USB 3, MIPI SLIMBus, SoundWire, CSI, DSI, UniPro, DigRF 100G Ethernet, XAUI, PON, SGMII, LTE, and WiGig. For more information on Cadence IP, please visit http://ip.cadence.com.

"The award recognition from TSMC further exemplifies that Cadence IP and tools can successfully enable customers to address their power, performance and area requirements for advanced SoC designs," said Dr. Chi-Ping Hsu, senior vice president and chief strategy officer for EDA at Cadence. "Our long-standing relationship with TSMC demonstrates our joint dedication to collaborating with customers who are at the forefront of these new process nodes."

"We presented these awards to Cadence based on its continued ability to provide quality of results via its analog/mixed-signal IP and 10nm FinFET solutions," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "We've worked closely with Cadence for many years on the development of advanced, reliable solutions for our mutual customers and look forward to furthering our collaboration to stay at the forefront of design innovations."

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.

© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, Denali, Spectre and Virtuoso are registered trademarks and Innovus, Quantus, Tempus and Voltus are trademarks of Cadence Design Systems, Inc. in the United States and other countries. PCIe is a registered trademark of PCI-SIG. All other trademarks are the property of their respective owners.

For more information, please contact:
Cadence Newsroom
408-944-7039
Email Contact

Logo - http://photos.prnewswire.com/prnh/20140102/SF39436LOGO

 

To view the original version on PR Newswire, visit: http://www.prnewswire.com/news-releases/cadence-receives-two-tsmc-partner-of-the-year-awards-for-10nm-finfet-solutions-and-analogmixed-signal-ip-300149478.html

SOURCE Cadence Design Systems, Inc.

Contact:
Cadence Design Systems, Inc.
TSMC
Web: http://www.cadence.com




Review Article Be the first to review this article
CST Webinar Series

EMA:

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Retail Therapy: Jump starting Black Friday
Peggy AycinenaIP Showcase
by Peggy Aycinena
REUSE 2016: Addressing the Four Freedoms
More Editorial  
Jobs
ACCOUNT MANAGER MUNICH GERMANY EU for EDA Careers at MUNICH, Germany
FAE FIELD APPLICATIONS SAN DIEGO for EDA Careers at San Diego, CA
AE-APPS SUPPORT/TMM for EDA Careers at San Jose-SOCAL-AZ, CA
Principal Circuit Design Engineer for Rambus at Sunnyvale, CA
Manager, Field Applications Engineering for Real Intent at Sunnyvale, CA
Development Engineer-WEB SKILLS +++ for EDA Careers at North Valley, CA
Upcoming Events
Zuken Innovation World 2017, April 24 - 26, 2017, Hilton Head Marriott Resort & Spa in Hilton Head Island, SC at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
CST Webinar Series



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy