New performances specified for minimizing Power Regulator Capacitances

Grenoble, France – Reducing the cost of Bill-of-Material (BoM) remains SoC Integrators' vital challenge for IoT applications, while minimizing power consumption demands the acute complexity of mode control for Dynamic Voltage and Frequency "Stepping" (DVFS). 

External capacitors and their associated pins are the first target for BoM reduction, up to the ultimate solution provided by capless regulators

To avoid any risk on output voltage stability during current peaks, which may result in a performance degradation of the load, referring  to the maximum current surge only (Ipeak)  is  insufficient . Dolphin Integration thus  introduces the missing specification by launching the  innovative template needed for embedding low BoM regulators, down to pinless, namely the dynamic  Load Current Tolerance Template (LCT2). 

It enables users to improve the resulting Load Transient performance, which is the property of the  regulator and of the  load

For optimizing the pairing of regulator and load, an  Abacus for adapting the load capacitance with filler capacitors must be provided.

Besides this issue of load steady-state functioning, its start-up sequence must be secured beyond a mere Imax by complying with the dynamic  In-rush Current Tolerance Template (ICT2).
The need of both LCT2 and ICT2 is acute:

  • to secure the  efficiency of regulators beyond guess-work
  • to optimize a  capless regulator for the load internal capacitance
  • to enable parallel development of loads and regulators with  template budgets
  • to make good use of the needed  abacus for optimizing the overall Load Transient performance.

The LCT2 is a must in the specification of any regulator, as well as the ICT2, such as specified for the  iLR-LaDiable

Overall, Dolphin Integration empowers SoC integrators to embed and to optimize the whole power network with its complete offering of  regulators, compliant with the  DELTA Standard.




Review Article Be the first to review this article
Aldec

Downstream : Solutuions for Post processing PCB Designs

Featured Video
Jobs
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Upcoming Events
Methodics User Group Meeting at Maxim Integrated 160 Rio Robles San Jose CA - Jun 5 - 6, 2018
2018 FLEX Korea at Room 402/ 403, COEX Seoul Korea (South) - Jun 20 - 21, 2018
IEEE 5G World FOrum at 5101 Great America Parkway Santa Clara CA - Jul 9 - 11, 2018
PCB WEST 2018 Conference & Exhibition at Santa Clara Convention Center Santa Clara CA - Sep 11 - 13, 2018
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL
DAC2018



Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise