TSMC Certifies Synopsys Design Tools for 10-nm FinFET Technology

Predictable Design Closure Enabled by the Galaxy Design Platform Now Available to Customers of TSMC 10-nm Process

MOUNTAIN VIEW, Calif., Sept. 17, 2015 — (PRNewswire) —

Highlights:

  • IC Compiler II certified for TSMC's 10-nm FinFET V0.9 process
  • Certification includes a new reference flow for the full suite of digital, signoff and custom implementation tools from the Galaxy Design Platform
  • Support for new technologies includes full coloring in implementation and extraction, and design-rule-driven custom layout to meet TSMC process requirements

Synopsys, Inc. (Nasdaq: SNPS) today announced that TSMC has certified the Synopsys GalaxyDesign Platform digital and custom design tools for TSMC's 10-nanometer (nm) FinFET process. The certification is based on the V0.9 version of the process and enables design engineering teams using TSMC's 10-nm process to realize the power of IC Compiler II's high throughput. Tool certification of V1.0 process is targeted to be completed Q4 2015. The certification includes routing rules, physical verification runsets, signoff-accurate extraction technology files, statistical timing analysis that correlates with SPICE, and interoperable process design kits (iPDKs) for FinFET processes. Built on a history of collaboration between TSMC and Synopsys, this certification ensures system-on-chip (SoC) designers can get optimum power, performance and area from the 10-nm process.

"Synopsys is ready with complete, certified, digital and custom implementation tools, as designers move to the 10-nanometer process," said Bijan Kiani, vice president of product marketing for Synopsys' Design Group. "This collaboration with TSMC for 10-nanometer ensures that the proven platform can be deployed for predictable design closure."

"Our deep and extensive collaboration with Synopsys on critical design-enablement technologies has continued beyond the 16nm FinFET Plus process," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "Synopsys and TSMC are addressing our customers' needs to deliver highly optimized design solutions for our most advanced 10-nm FinFET process."

Key Synopsys tools certified by TSMC include:

  • IC Compiler II: Certified by TSMC for V0.9 version of the 10-nm process with immediate availability of technology files and implementation collateral
  • IC Validator: Fully color-aware signoff physical verification for FinFET designs
  • StarRC extraction solution: Support for 10-nm multi-patterning, full color-aware variation modeling and 3-D FinFET modeling to enable industry-leading signoff accuracy
  • PrimeTime® timing signoff solution: Support for 10-nm low voltage with advanced waveform propagation, Liberty Variation Format (LVF)-based process variation and advanced placement rule engineering change order (ECO) guidance to accelerate timing closure and leakage recovery
  • PrimeRail: Accurate gate-level static and dynamic IR-drop analysis, color-aware electro-migration (EM) and power/ground (P/G) EM rules support
  • NanoTime: SPICE-accurate transistor-level static timing analysis of 10-nm embedded SRAMs
  • Galaxy Custom Designer® schematic editor and Laker® Layout Editor: Support for full coloring flow; track-pattern support, in-design EM/IR calculation and integration with CustomSim EM/IR analysis for debugging signoff errors in the layout
  • HSPICE®, CustomSim and FineSim® simulation products: Support for 10-nm FinFET device modeling with self-heating effect and delivery of accurate circuit simulation results for analog, logic, high-frequency and SRAM designs
  • CustomSim also supports 10-nm EM rules for accurate transistor-level EM and IR-drop analysis

In addition, TSMC also collaborates with Synopsys on DesignWare® STAR Memory System® product for test, repair and diagnostics of FinFET-based memories.

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 16th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP, and is also growing its leadership in software quality and security solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest quality and security, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.

Editorial Contacts:
Sheryl Gulizia
Synopsys, Inc.
650-584-8635
Email Contact

Lisa Gillette-Martin
MCA, Inc.
650-968-8900 ext. 115
Email Contact

 

To view the original version on PR Newswire, visit: http://www.prnewswire.com/news-releases/tsmc-certifies-synopsys-design-tools-for-10-nm-finfet-technology-300144720.html

SOURCE Synopsys, Inc.

Contact:
Synopsys, Inc.
Web: http://www.synopsys.com




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