The SERDES has been validated in SMIC 40nm process- silicon results are shown on the company web site including the TX Eye Diagram and the RX Jitter Tolerance tests.
“SilabTech USB 3.1 release marks another milestone in the company’s low power design and innovation tradition”, said Sujoy Chakravarty, CEO of SilabTech; “We are proud of our USB 3.1 power and area numbers and that it can be incorporated into high end SOC applications.”
SilabTech is working with USB Controller vendors to present an integrated PHY solution to the market that will ease SOC customers during integration and validation.
SilabTech’s USB 3.1 SERDES is designed to work with all physical connector types as per the USB standard, including Type C which is getting adopted in the PC, Storage and Consumer Electronics markets. The new USB 3.1 SERDES comes with a host of programmable parameters including Transmit Driver output swing, Pre/Post Cursor Transmit Equalization Range, Adaptive Receiver equalization (CTLE + DFE) and others. The IP has an embedded low-jitter Phase-Locked-Loop (PLL).
SilabTech is a privately held company, headquartered in Bengaluru , India with sales offices in US, Europe and China. The company was established in 2012 to bring innovative design approaches to the ever increasing challenge of on-board and backplane high speed connectivity. The company is led by a group of senior mixed signal designers with vast experience in building analog and mixed signal IPs and in integrating them at chip level. Among the company’s customers are multinational fabless IC companies, system companies and ASIC design houses. SilabTech has taped out multiple SERDES, High Speed ADCs and other Analog IP Cores in technologies ranging from 130nm to 28nm in multiple foundries.
Payal Chakraborty, Manager-Marketing Communications