Barco Silex releases new patent-free and lightweight VC-2 LD video codec at IBC 2015

Louvain-la-Neuve, Belgium -- At IBC 2015 Show in Amsterdam, Barco Silex, the leading provider of video compression IP cores for ASIC and FPGA, announced that the new VC-2 Low Delay codec is now available for licensing to broadcast equipment manufacturers.

The VC-2 Low Delay codec is a patent-free lightweight compression codec ideally suited to encode high-definition video content. VC-2 LD has ultra-low latency and compresses video streams by a compression ratio of 4 times visually lossless.

Originally developed by the BBC Research as Dirac Pro and later standardized as SMPTE 2042, the VC-2 LD codec is patent-free which will facilitate market adoption and interoperability. The SMPTE ST-2047 standard already defines the carriage of high resolution video (up to 1080p60) over HD-SDI using VC-2 LD as a mezzanine compression algorithm. The RTP mapping of the codec is also currently being standardized as an IETF RFC in order to maximize interoperability of the transport over IP networks.

VC-2 Low Delay will enable cost saving associated to the transport of high resolution and high frame rate video content. For example, a 1080p60 stream can be transported over a single 1Gbps Ethernet cable, and up to three 4K/UHD stream at 60 fps can be transported over 10Gbps cable.

“A key distinguishing feature of VC-2 is that it is an open technology designed to avoid patent infringements. So it can be easily included in video production equipment as a hardware or software solution, without the potential costs, uncertainties, and practical difficulties of including other proprietary codecs” says Jean-Marie Cloquet, product manager of the video division at Barco Silex.

Barco Silex will demonstrate the VC2 LD codec on FPGA during IBC show (booth 10.D31a).

Get more information about the VC-2 Low Delay codec at:  http://www.barco-silex.com/ip-cores/vc2-codec

About Barco Silex

Barco Silex is the market leader in video processing and security IP cores and platforms as well as electronic design services (ASIC, FPGA, DSP, Board). The full-range of Barco Silex JPEG 2000 and VC-2 LD IP cores enable high-performance and high-quality coding and support a wide range of features and options: ultra-low latency, lossless compression, high resolution (UHD/4K) and more.




Review Article Be the first to review this article

ALDEC:

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Reverie: All That Glitters is not Past
More Editorial  
Jobs
Technical Support Engineer for EDA Careers at Freemont, CA
Development Engineer-WEB SKILLS +++ for EDA Careers at North Valley, CA
Senior Physical Design Engineer for Ambiq Micro at Austin, TX
FAE FIELD APPLICATIONS SAN DIEGO for EDA Careers at San Diego, CA
Digital and FPGA Hardware Designer for Giga-tronics Incorporated at San Ramon, CA
Technical Marketing Manager Valley for EDA Careers at San Jose, CA
Upcoming Events
Zuken Innovation World 2017, April 24 - 26, 2017, Hilton Head Marriott Resort & Spa in Hilton Head Island, SC at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
2017 IoT Developers Conference at Santa Clara Convention Center California - Apr 26 - 27, 2017
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy