Synopsys' IC Validator Distributed Processing Accelerates Signoff Physical Verification of Mellanox Design

IC Validator Delivers Near-Linear Distributed Processing Scalability

MOUNTAIN VIEW, Calif., Aug. 31, 2015 — (PRNewswire) —

Highlights:

  • IC Validator used for full foundry signoff DRC, LVS and DFM verification
  • Delivered near-linear distributed processing scaling on 100+ million-instance design
  • Included customized DFM rule verification for added reliability

Synopsys, Inc. (Nasdaq: SNPS) today announced that IC Validator used advanced multi-processing techniques to speed up the design rule checking (DRC) of Mellanox's latest design. IC Validator completed the signoff physical verification using TSMC's 28nm signoff runset and reduced the DRC elapsed time for this large design to under 14 hours by automatically distributing the job over 28 processor cores. IC Validator's high-productivity multi-processing was also used to speed up layout versus schematic (LVS) correctness checking and to perform customized design for manufacturability (DFM) and dummy metal fill on the design.

"We ran our design on 28 processor cores and found IC Validator to deliver near-linear scalability, reducing DRC run time," said Ofer Ezra, principal engineer at Mellanox. "We achieved further productivity gains by writing a customized dummy metal fill runset for IC Validator that gave us additional reliability advantages on our on-chip power distribution network."

IC Validator is a comprehensive physical verification product including design rule checks (DRC), layout-vs.-schematic (LVS) checks, double-patterning checks and metal fill insertion. IC Validator's modern architecture and excellent multi-core scalability make it the signoff tool of choice for a growing number of designers developing small analog chips to those designing the largest, most advanced digital chips.

"A growing number of companies are seeing the benefits of physical verification signoff with IC Validator," said Bijan Kiani, vice president of marketing for Synopsys' Design Group. "The successful tapeout of this large design reinforces the viability of IC Validator as a signoff product that enables significantly reduced time to tapeout for our customers."

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 16th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP, and is also a leader in software quality and security testing with its Coverity® solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest quality and security, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.

Editorial Contacts:
Sheryl Gulizia
Synopsys, Inc.
650-584-8635
Email Contact

Lisa Gillette-Martin
MCA, Inc.
650-968-8900 ext. 115
Email Contact

 

To view the original version on PR Newswire, visit: http://www.prnewswire.com/news-releases/synopsys-ic-validator-distributed-processing-accelerates-signoff-physical-verification-of-mellanox-design-300134892.html

SOURCE Synopsys, Inc.

Contact:
Synopsys, Inc.
Web: http://www.synopsys.com




Review Article Be the first to review this article
Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
ICScape: At the Junction of Math & CS, EDA & IP
Peggy AycinenaIP Showcase
by Peggy Aycinena
Arm Momentum: Segars embraces exciting times
More Editorial  
Jobs
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, Germany
REVISED***Director Product Line RF/IC for EDA Careers at San Jose, CA
Senior SW Developer for EDA Careers at San Jose, CA
Upcoming Events
“Empowering Leadership with WIT and WISDOM” at SEMI 673 South Milpitas Blvd. Milpitas CA - Nov 28, 2017
Artificial Intelligence and Convolution Neural Networks Discussion at San Jose State University Student Union Theater San Jose CA - Dec 4, 2017
Silicon Valley's Only Comprehensive Embedded Systems Conference at San Jose Convention Center 150 W. San Carlos St. San Jose CA - Dec 5 - 7, 2017
Oski Technology’s Decoding Formal Club Meeting at The Conference Center San Jose CA - Dec 7, 2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise