Dolphin Integration and TSMC collaborate on Low-Power IoT Subsystem Design

Grenoble, France – Dolphin Integration today announced a collaborative effort with TSMC to ease the design and optimization of Internet of Things (IoT) subsystems for System-on-Chip (SoC) integrators.

Ultra-low power requirements combined with shortened time-to-market windows highlight the needs to reduce design methodology complexity and to simplify Silicon IP component integration. Leveraging TSMC’s ultra-low power technology, Dolphin Integration is introducing a number of innovations that will provide low-power SoC designers with enhanced support:

A complete  Low-power Panoply (LoPan)

  • A low-leakage library for always-on logic and a low dynamic-power library for most of the area.
  • A straightforward Island Construction Kit (ICK) to implement power islands ready for temporary extinction or retention with no need for iterative tuning.
  • The ICK empowers not only Dolphin's low-power library but also the foundry's library for high speed islands.

Dynamic management of power regulators

Guidelines for consistent clock and voltage domains

  • Key design and SoC integration guidelines along with complementary design flows for guiding clock-gating, consistent with power modes of islands.

Configurable synchronous control networks

  • A configurable island control network, Maestro, acting as a practical substitute for any complex asynchronous scheme, and for easily building and controlling power domains and their regulators.

To demonstrate the improvements enabled in the control of power islands and the dynamic interplay of individual components typically embedded in an IoT SoC, Dolphin Integration will provide results of TAISHAN, a TSMC 55 nm ULP Demo Chip.

“Leading-edge More-Than-Moore process variants, like TSMC's ultra low-power process at 55nm, and the design challenges of IoT and wearable devices, deserve equally state-of-the-art design methodologies,” said Dolphin Integration CTO, Gilles Depeyrot.  “It involves libraries of Silicon IPs for embedded voltage regulation and for the SoC mode control network. The reference sub-system also demonstrates the integration and verification of power domains to reach extreme performances. We have extended the practice of testchips to ‘reference sub-system designs’ demonstrating and popularizing such advanced capabilities.”

“In order to simplify our customers’ designs and shorten their time-to-market, TSMC and its ecosystem partners are transitioning from chip-design enablers to subsystem enablers,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “We will offer technology, subsystem reference designs and packaging options to deliver straightforward solutions for the rapidly expanding IoT and consumer device markets.”




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