MEDIA ALERT: Cadence to Showcase IP and Processor Technology at 2015 Flash Memory Summit

SAN JOSE, Calif., Aug. 4, 2015 — (PRNewswire) — Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that it plans to exhibit its latest intellectual property (IP) and processor technologies at this year's Flash Memory Summit at booth 616 from August 11 to 13, 2015, in Santa Clara, CA. 

Cadence Logo

WHO:
Cadence is scheduled to demonstrate its latest flash memory IP, verification models, and Tensilica® offload processor optimization for flash, which serves as the crucial component for many products in the consumer, computer and enterprise markets.

WHEN:
Tuesday, August 11, through Thursday, August 13, 2015

WHERE:
Booth 616 at the Flash Memory Summit
Santa Clara Convention Center
Santa Clara, CA

WHAT:
Cadence is offering a variety of opportunities to learn about the latest trends in IP and to interact with technology experts, users and partners. These include the following:

Cadence demonstrations in Booth 616:

  • Latest ONFi and eMMC IPVerification memory models for the latest standards
  • Tensilica offload processor optimization for flash

A Cadence-sponsored event:

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at http://www.cadence.com.

© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Tensilica and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

For more information, please contact:
Cadence Newsroom
(408) 944-7039
Email Contact

Logo - http://photos.prnewswire.com/prnh/20140102/SF39436LOGO

 

To view the original version on PR Newswire, visit: http://www.prnewswire.com/news-releases/media-alert-cadence-to-showcase-ip-and-processor-technology-at-2015-flash-memory-summit-300121756.html

SOURCE Cadence Design Systems, Inc.

Contact:
Cadence Design Systems, Inc.
Web: http://www.cadence.com




Review Article Be the first to review this article
Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Job Openings: Can EDA Predict the Future
More Editorial  
Jobs
Engr, Elec Des 2 for KLA-Tencor at Milpitas, CA
Timing Design Engineer(Job Number: 17001757) for Global Foundaries at Santa Clara, CA
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
Senior FPGA Designer for Fidus Electronic Product Development at Fremont, CA
Test Development Engineer(Job Number: 17001697) for Global Foundaries at Santa Clara, CA
Upcoming Events
CDNLive Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Apr 11 - 12, 2017
10th Anniversary of Cyber-Physical Systems Week at Pittsburgh, PA, USA PA - Apr 18 - 21, 2017
DVCon 2017 China, April 19, 2017, Parkyard Hotel Shanghai, China at Parkyard Hotel Shanghai Shanghai China - Apr 19, 2017
Zuken Innovation World 2017 at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
S2C: FPGA Base prototyping- Download white paper



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy