Toshiba Standardizes on PrimeRail for Rail Signoff

Superior Performance and Accuracy, Combined with In-Design Early Analysis Boosts Design Teams' Productivity

MOUNTAIN VIEW, Calif., June 3, 2015 — (PRNewswire) — Highlights:

  • PrimeRail exceeded Toshiba's rigorous accuracy qualification criteria for static rail analysis
  • Toshiba saw 1.5X faster runtimes and 30 percent smaller memory footprint over the reference solution
  • Synopsys' In-Design seamless integration capabilities of PrimeRail and IC Compiler significantly improves turnaround time
  • Toshiba has deployed PrimeRail static signoff analysis globally in its implementation and signoff kit

Synopsys, Inc. (Nasdaq: SNPS) today announced that Toshiba Corporation has adopted and successfully deployed the Synopsys PrimeRail analysis tool as the rail signoff solution for static analysis. PrimeRail signoff will be used for all of Toshiba's product lines, including mixed signal, ASIC and memories.

"Rail analysis has become a critical requirement for advanced technology nodes," said Mr. Kazunari Horikawa, senior manager of Design Technology Development Department, Mixed Signal IC Division at Toshiba Corporation Semiconductor and Storage Products Company. "Synopsys PrimeRail provides 1.5X faster performance over the existing solution and accuracy that meets our stringent signoff requirements. It also offers an extensive set of features to support Toshiba's broad variety of design styles and technologies.  In-Design early analysis during design implementation made it easy for designers to build a robust power grid early. This early analysis combined with silicon proven accuracy and faster performance allows us to save multiple weeks in our schedules and sign off with confidence."

Built on Synopsys' PrimeTime® timing and power engines, PrimeRail leverages industry-proven technology to provide SPICE-accurate static and dynamic rail analysis. The multi-threaded and highly scalable engine is able to analyze 100 million instances overnight, while native support for multi-voltage, complex I/O cells, analog blocks and external IP provides full chip analysis capabilities. Seamless IC Compiler™ and PrimeRail In-Design integration makes power and voltage drop analysis easily accessible during implementation to help address PG network weaknesses early in the flow, and to minimize costly last-minute engineering change orders (ECOs).

"Toshiba put PrimeRail through a rigorous qualification process on multiple production designs at Toshiba and it consistently exceeded Toshiba's signoff criteria," said Bijan Kiani, vice president of marketing for Synopsys' Design Group. "With the release and standardization of PrimeRail in the physical implementation kit for early analysis and signoff, Toshiba design teams see a significant productivity boost for their advanced and established node designs."  

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP, and is also a leader in software quality and security testing with its Coverity® solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest quality and security, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.

Editorial Contacts:
Sheryl Gulizia
Synopsys, Inc. 
650-584-8635 
Email Contact

Lisa Gillette-Martin
MCA, Inc.
650-968-8900 ext. 115
Email Contact 

 

To view the original version on PR Newswire, visit: http://www.prnewswire.com/news-releases/toshiba-standardizes-on-primerail-for-rail-signoff-300093230.html

SOURCE Synopsys, Inc.

Contact:
Synopsys, Inc.
Toshiba Corporation
Web: http://www.synopsys.com




Review Article Be the first to review this article

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
H-1B Visa: de Geus’ tragedy looms large
Peggy AycinenaIP Showcase
by Peggy Aycinena
IP for Cars: Lawsuits are like Sandstorms
More Editorial  
Jobs
Staff Software Engineer - (170059) for brocade at San Jose, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Mechanical Designer/Engineer for Palo Alto Networks at Santa Clara, CA
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
ASIC/FPGA Design Engineer for Palo Alto Networks at Santa Clara, CA
Upcoming Events
Embedded Systems Conference ESC Boston 2017 at Boston Convention & Exhibition Center Boston MA - May 3 - 4, 2017
2017 GPU Tech Conference at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - May 8 - 11, 2017
High Speed Digital Design and PCB Layout at 13727 460 Ct SE North Bend WA - May 9 - 11, 2017
Nanotech 2017 Conference & Expo at Gaylord National Hotel & Convention Center WA - May 14 - 17, 2017
Verific: SystemVerilog & VHDL Parsers
DAC2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy