So-ADE Unveils Debugger for Use with Verific Design Automation’s SystemVerilog, VHDL, UPF Parser Platforms

So-ADE Debugger Developed to be Easy to Use, Intuitive

SAINT GEOIRE EN VALDAINE, FRANCE –– May 21, 2015 –– So ADE™todayannouncedimmediate availability of an easy-to-use and intuitive debugger for the development and debugging of theSystemVerilog, VHDL and UPF parser platform from Verific Design Automation.

Meant for C/C++ developers, So-ADE adds electronic design automation (EDA) concept knowledge tothe debugger level. It automatically manipulates the Abstract Syntax Tree (AST) from VHDL, Verilog or SystemVeriloghardware description languages, parsing for faster code development and algorithm debug with commonly used data structures.

“We’re delighted that So-ADE created a product around our parser platform, and they have our full support,” notes MichielLigthart, Verific’s president and chief operating officer. “Today’s announcement reinforces Verific’s reach as the industry standard for SystemVerilog and VHDL based EDA tools, such as analysis, emulation, simulation and synthesis.”

The So-ADE debugger includes built-in support for all ASTs generated by Verific’s parser platform. The debugger is able to navigatean AST from any program break point, allowing a user who may not be familiar with an AST structure to analyze it.

Compliant with netlist-level program debuggers through an application programming interface (API), it extracts netlist information directly from any debugged program and displays a schematic through its rendering engine. So-ADE facilitates stack analysis and analyzes algorithm behavioral.

“Our tool was developed to be easy to use and efficient, which is why we elected to work with Verific, a company noted for quality software, support and service,” states Stephane Petithomme of So-ADE.

The EDA and field programmable gate array (FPGA) industry relies onVerific’s software to serve as the front end for tools used for analysis, simulation, verification, synthesis, emulation and test of register transfer level (RTL) designs. Its Parser Platform includes support for SystemVerilog, Verilog, VHDL and UPF, and provides C++, Python and Perl APIs. Verific’s software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux and Windows operating systems.

Verific will exhibit at the 52nd Design Automation Conference (DAC) in booth (#2714) June 8-June 10at theMoscone Center, San Francisco. Information about DAC can be found at: www.dac.com

About Verific Design Automation

Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides parsers and elaborators for SystemVerilog, Verilog, VHDL and UPF. Verific’s software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 60,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Email: Email Contact Website: www.verific.com

About So-ADE

Founded in 2015, So-ADE is a privately held company Saint GeoireEnValdaine, France, developing and marketing innovative consulting services for electronic design automation (EDA) software suppliers, in-house CAD tool developers and semiconductor companies. Its primary products are So ADE graphengine, a schematic generator available at the C++ source code level, and So ADE debugger, a cutting-edge C/C++ EDA tool debugger. Email: Email Contact Website: www.so-ade.com


Contact:

Nanette Collins
Public Relations for Verific
(617) 437-1822
Email Contact




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