ClioSoft to Demonstrate SOS Design Data Management Platform at CDN LIVE EMEA 2015 in Germany

CERN to present on IC design project data management for high-energy physics

FREMONT, Calif., April 24, 2015 – ClioSoft, Inc., a leader in system-on-chip (SoC) design data and intellectual property (IP) management solutions for the semiconductor design industry, will showcase its SOS design management platform at CDN Live EMEA in Munich, Germany, on April 27-29, 2015. In addition, Wojciech Bialas, PhD, from the European Organization for Nuclear Research ( CERN), a customer of ClioSoft’s, will present on integrated circuit (IC) design project data management on April 29th.

The SOS design management platform is tightly coupled with the Cadence® Virtuoso® platform to empower design engineers to manage design data directly from the Virtuoso cockpit.  In addition to the SOS design management platform, ClioSoft also will demonstrate the Visual Design Diff software, which displays design differences in schematics, layout and RTL. This is particularly useful in ECO flows to track the changes made between different versions of the same design on which different design engineers are working.


The SOS platform from ClioSoft provides SoC design data and IP management to streamline the design process. SOS facilitates multi-site design collaboration and includes, among other features, integrated revision control, release and derivative management and interface to commonly-used bug tracking systems. At EMEA, ClioSoft will showcase how the tight integration of ClioSoft’s SOS with the Cadence Virtuoso design flow improves design team productivity by providing data management and tool features from the same cockpit. This helps reduce the possibility of design re-spins due to incorrect configurations.

Visual Design Diff (VDD) from ClioSoft gives users the power to quickly compare two versions of a schematic or layout by graphically highlighting the differences directly in their own design editors. A hierarchical diff option allows all differences for the entire design hierarchy below the selected view to be flagged.

To view a joint ClioSoft/ Cadence webinar showcasing improved collaboration within dispersed design teams using Cadence Virtuoso libraries, PDKs, and design IPs, click here.


Session Title: IC design project data management

Session Abstract:

It is not rare that the problem of design data management is left underestimated by project managers and/or design engineers. Ad hoc methodologies that worked in the past among IC design project members do not necessarily work correctly today, since the complexity of designs and process design kits only increases with time, accompanied by a rise in the number of people needed to successfully accomplish the design process. The problem is even more pronounced when project resources, both human and technical, are geographically and/or institutionally dispersed, also not uncommon in today's academic, R&D and business environments. This paper will present current existing solutions to these problems based on work methodology change and software tools available on the market. The staff training or class teaching component will also be addressed as necessary response to work methodology evolution. Practical examples of successful transitions from unmanaged to managed data projects will be presented based on the experience of the High Energy Physics community, where institutes involved in ASIC projects targeting for Large Hadron Collider (LHC) experiments and accelerator machine upgrade programs are often widely dispersed geographically. The adopted solution makes use of the SOS software suite from ClioSoft Inc.


Wojciech Bialas was born in Krakow, Poland. He received the M.Sc. in electronic engineering degree in 1992 and the M.Sc. in Computer Science degree in 1996, both from the AGH UST in Krakow, followed by a Ph.D. degree from the same university in 1999. Since 2001 he has worked in microelectronics group at the European Organization for Nuclear Research (CERN) on development of full custom VLSI electronics for physics experiments. He is also responsible for CAD/CAE software tools deployment and maintenance, with 13 years experience in this field.

WHEN: CDN LIVE EMEA will take place on April 27-29th, 2015. The CERN presentation will take place from 11:30am – 12:00 on April 29th.

WHERE: CDN Live EMEA will be held in the Dolce Hotel Unterschleissheim 
Munich, Germany.

WHO:  Of interest to digital, analog & RF designers, and CAD engineers/managers.

About ClioSoft

ClioSoft is the premier developer of hardware configuration management (HCM) solutions for digital, analog, RF and mixed-signal designs. The company's SOS Design Collaboration Platform is built to handle the complex requirements of system-on-chip design flows. The SOS platform provides a sophisticated multi-site development environment that enables global team collaboration and efficient management of design data from concept through tape-out along with an enterprise IP management and design reuse solution. SOS is integrated with leading design flows –Cadence’s Virtuoso® technology, Keysight Technologies’ Advanced Design System (ADS), Mentor Graphic’s Pyxis Custom IC Design, Synopsys’ Galaxy Custom Designer® and Laker3™ Custom Design.

All trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

#          #          #

Media Contact:

Linda Marchant
Cayenne Communication
Email Contact




Read the complete story ...

Review Article Be the first to review this article
Downstream : Solutuions for Post processing PCB Designs

Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
H-1B Visa: de Geus’ tragedy looms large
Peggy AycinenaIP Showcase
by Peggy Aycinena
IP for Cars: Lawsuits are like Sandstorms
More Editorial  
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Mechanical Designer/Engineer for Palo Alto Networks at Santa Clara, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
ASIC/FPGA Design Engineer for Palo Alto Networks at Santa Clara, CA
CAD/CAM Regional Account Manager (Pacific Northwest) for Vero Software Inc. at Seattle, WA
Upcoming Events
Embedded Systems Conference ESC Boston 2017 at Boston Convention & Exhibition Center Boston MA - May 3 - 4, 2017
2017 GPU Tech Conference at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - May 8 - 11, 2017
High Speed Digital Design and PCB Layout at 13727 460 Ct SE North Bend WA - May 9 - 11, 2017
Nanotech 2017 Conference & Expo at Gaylord National Hotel & Convention Center WA - May 14 - 17, 2017
Verific: SystemVerilog & VHDL Parsers

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy