SilabTech announces the release of its JESD204B Compliant 12.5Gbps SERDES PHY and Controller

Bengaluru (India) – March 4, 2015 -SilabTech, leading supplier of High Speed Interface intellectual property designs (IPs), announced today the release of its JESD204B SERDES PHY and Controller.  SilabTech has already delivered this JESD204B SERDES and Controller to its early licensees including a top tier semiconductor company.   These products SERDES has been validated in the TSMC 28nm HPM process, while the controller is a soft IP designed to support a wide range of process technology nodes.

“In addition to being a silicon-proven solution for JESD204B, the SilabTech SERDES  is reported by our customers to have significantly lower power consumption than the competitors’ offerings”, said Sujoy Chakravarty, CEO of SilabTech; “SilabTech is also flexible to license the JESD204B Controller for use with our customer’s SERDES or as a completely verified and integrated solution with the SilabTech SERDES.”  This 12.5Gbps SERDES supports multiple interface standards including:  PCIe Gen1/2/3, USB3.0, CEI-11G-SR and JESD204B.  The IP functional mode is easily configured via an APB interface provided by SilabTech and the data rate is programmable from 1.25 – 12.5 Gbps.

This release is significant to the SOC design community and especially to design engineers who look for a simplified way to enable high speed on-board networking. “We are delighted to offer our customers  integrated solutions of high speed, low power SERDES and Controllers which readily enable them to build the next generation products”, said Sujoy. In addition, other SERDES parameters can be programmed such as the Transmit Driver output swing, Pre/Post Cursor Transmit Equalization Range, Adaptive Receiver equalization (CTLE + DFE) and others. The IP has an embedded low jitter Phase-Locked-Loop (PLL).

JESD204B is a JEDEC interconnect standard that enables chip-to-chip connectivity at speeds that exceed 10 Gb/Sec per  lane.  SilabTech SERDES can be deployed in a multi-lane configuration such as 8 Tx and 8 Rx lanes to enable 100+Gb/Sec connectivity. The IP main application is SOC connectivity to High Sampling Rate ADCs (Analog to Digital Converter) and DACs (Digital to Analog Converter) in RF, Optical, Measurement and Communication boards.

This JESD204B release enhances SilabTech’s existing SERDES offerings and  is available in technologies of multiple foundries such as TSMC, Global Foundries and SMIC.

About Silab Tech:

Silab Tech is a privately held company, HQ in Bangalore India with sales offices in US, Europe and China. The company was established in 2012 to bring innovative design approaches to the ever increasing challenge of on-board and Backplane high speed connectivity. The company is led by a group of senior analog designers with vast experience in building analog and mixed signal IPs and in integrating them at chip level. Among the company customers are multinational fabless IC companies, system companies and ASIC design houses. SilabTech has taped out multiple SERDES designs in the last year itself.

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