Leti’s Latest Compact Model for UTBB-FDSOI Technology Now Available in All Major Spice Simulators

Leti-UTSOI2.1, Offering Improved Predictability and Accuracy, Will Be Presented March 12 at MOS-AK Workshop During DATE 2015 in Grenoble

GRENOBLE, France – March 11, 2015 - CEA-Leti today announced the newest version of its advanced compact model for UTBB-FDSOI technology is now available in all major SPICE simulators.

Leti-UTSOI2.1 improves the predictability and accuracy capabilities of the Leti-UTSOI2 compact model, which was developed in 2013 to describe the electrical behavior of FDSOI transistors by taking into account all their specificities. It was the first available compact model capable of describing and accurately predicting the behavior of UTBB-FDSOI transistors in all bias configurations, including strong forward bias applied to the back gate of the device.

Fully Depleted Silicon On Insulator (FDSOI) is a planar process technology that relies on two primary innovations. First, an ultra-thin layer of insulator, called the buried oxide, is positioned on top of the base silicon. Then, a very thin silicon film implements the transistor channel. Thanks to its thinness, there is no need to dope the channel, thus making the transistor fully depleted. The combination of these two innovations is called “ultra-thin body and buried oxide Fully Depleted SOI” or UTBB-FDSOI.

The Leti-UTSOI2 compact model solution offers designers an essential tool to take full advantage of FD-SOI technology specificities in power consumption and performance optimization.

“This new version of the ultra-thin SOI model, which affirms Leti’s continuing leadership in FD-SOI technology, is ideal for designers seeking differentiation in energy management and performance for advanced nodes,” said Leti CEO Marie-Noëlle Semeria.

The model considerably extends the domain of physical device description compared to other solutions. To provide this feature, Leti used a unique analytical resolution scheme for the calculation of surface potentials at both interfaces of the transistor body, which is valid for all kinds of independent double-gate transistors. From this analytical resolution, Leti has developed the complete model in collaboration with STMicroelectronics, and Leti-UTSOI2 is now used in industrial design kits.

Leti-UTSOI2.1 further improves predictability and accuracy. These improvements include a direct and predictive link between bi-dimensional device electrostatics and process parameters, a refined description of narrow-channel effects, improved accuracy of moderate inversion regime and gate tunneling current modeling.

Leti-UTSOI2.1 is now available in most of the commercial SPICE and Fast SPICE simulators used by industry.

Thierry Poiroux, Leti research engineer and model co-developer, will present the new model at the MOS-AK workshop,  “New version of Leti-UTSOI2 featuring further improved predictability”, at 2:30 p.m. March 12, during DATE 2015.

About CEA-Leti (France)

As one of three advanced-research institutes within the CEA Technological Research Division, CEA-Leti serves as a bridge between basic research and production of micro- and nanotechnologies that improve the lives of people around the world. It is committed to creating innovation and transferring it to industry. Backed by its portfolio of 2,800 patents, Leti partners with large industrials, SMEs and startups to tailor advanced solutions that strengthen their competitive positions. It has launched 54 startups. Its 8,500m² of new-generation cleanroom space feature 200mm and 300mm wafer processing of micro and nano solutions for applications ranging from space to smart devices. With a staff of more than 1,800, Leti is based in Grenoble, France, and has offices in Silicon Valley, Calif., and Tokyo. Follow us on www.leti.fr and @CEA_Leti.

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