MaxLinear Achieves Significant Area Savings and Turnaround Time Reduction Using Cadence Innovus Implementation System

SAN JOSE, Calif., March 10, 2015 — (PRNewswire) —  Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that MaxLinear, Inc. (NYSE: MXL) used the Cadence® Innovus Implementation System on a multi-million instance 28 nanometer chip, significantly improving both area and turnaround time. Leveraging the capacity and runtime advantage of the Innovus Implementation System, MaxLinear was able to move from a hierarchical methodology to a flat design flow, achieving 10 percent die-size area savings using a minimum number of metal layers. MaxLinear also reduced runtime from four-and-a-half days to just over a day when compared with its previous solution.

Cadence Logo.

The Innovus Implementation System provides high-quality placement optimization via the new GigaPlace placement engine, which enabled MaxLinear to implement multi-million cell blocks while realizing significant die-size area savings. In addition, Innovus Implementation System features core algorithms, including for placement, that have been enhanced with multi-threading to provide significant speedup on industry-standard hardware with 8 to 16 CPUs.

"Our products enable the reception of broadband data and video content, requiring high levels of performance, small silicon die-size, and rapid time to market," said Dr. Paolo Miliozzi, senior director, SOC Technology and Physical Design at MaxLinear. "Innovus Implementation System has provided us with unprecedented full-flow speed-up, so we can deliver reliable designs to market faster. Moving to a flat design flow using Innovus Implementation System enabled significant area gains while reducing the turnaround time to about a day."

"The Innovus Implementation System was designed to improve the overall productivity of physical design engineering teams, and we've seen many customers, including MaxLinear, improve both quality of results and turnaround time simultaneously," said Dr. Anirudh Devgan, senior vice president of the Digital and Signoff Group at Cadence. "Achieving die-size area savings and significantly faster runtime enabled reduced development costs for these large designs."

For more information on the Innovus Implementation System, the Cadence next-generation physical implementation solution, please visit Also, see today's related press release titled, "Cadence Introduces Innovus Implementation System, Delivering Best-in-Class Results with Up to 10X Reduction in Turnaround Time," at

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at

© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks and Innovus is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

For more information, please contact:
Cadence Newsroom
Email Contact

Logo -


To view the original version on PR Newswire, visit:

SOURCE Cadence Design Systems, Inc.

Cadence Design Systems, Inc.
MaxLinear Inc.

Review Article Be the first to review this article

Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
H-1B Visa: de Geus’ tragedy looms large
Peggy AycinenaIP Showcase
by Peggy Aycinena
IP for Cars: Lawsuits are like Sandstorms
More Editorial  
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
ASIC/FPGA Design Engineer for Palo Alto Networks at Santa Clara, CA
Mechanical Designer/Engineer for Palo Alto Networks at Santa Clara, CA
Technical Support Engineer for EDA Careers at Freemont, CA
CAD/CAM Regional Account Manager (Pacific Northwest) for Vero Software Inc. at Seattle, WA
Upcoming Events
Embedded Systems Conference ESC Boston 2017 at Boston Convention & Exhibition Center Boston MA - May 3 - 4, 2017
2017 GPU Tech Conference at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - May 8 - 11, 2017
High Speed Digital Design and PCB Layout at 13727 460 Ct SE North Bend WA - May 9 - 11, 2017
Nanotech 2017 Conference & Expo at Gaylord National Hotel & Convention Center WA - May 14 - 17, 2017

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy