Synopsys Galaxy Design Platform Enables 90 Percent of Volume-Production FinFET Designs

Vast Majority of Designers Choose Synopsys Implementation Tools for Move from Test Chips to Production Tapeout

MOUNTAIN VIEW, Calif., March 10, 2015 — (PRNewswire) —  

Highlights:

  • Galaxy Design Platform used for 90 percent of production FinFET designs
  • Strong platform adoption underscores Synopsys' leadership in digital and custom design implementation tools for FinFET
  • All FinFET foundries have used and qualified the Galaxy Design Platform

Synopsys, Inc. (Nasdaq: SNPS) today announced that its Galaxy Design Platform enables 90 percent of the production tapeouts of FinFET-based designs. Over 20 industry leaders worldwide have successfully completed more than 100 FinFET tapeouts using the platform.  Foundries including GLOBALFOUNDRIES, Intel Custom Foundry, Samsung and others have implemented test chip and production FinFET tapeouts with Galaxy Design Platform for mutual customers including Achronix, Global Unichip Corporation (GUC), HiSilicon Technologies, Marvell, Netronome, NVIDIA, Samsung and others, representing a broad spectrum of application markets, including consumer electronics, wireless, graphics, microprocessor and networking devices.

FinFET-based process nodes offer a number of advantages including greater density, lower power and higher performance. New, innovative technologies in the Galaxy Design Platform implementation tools seamlessly handle the myriad new design rules associated with the shift from planar to 3D transistors to enable these advantages. Synopsys has engaged in comprehensive collaboration with foundry partners to ensure all the tools in the Galaxy Design Platform have been updated to support the process changes introduced by FinFET devices including multi-patterning and local interconnect structures. The updated tools include the Design Compiler® synthesis solution, TetraMAX® ATPG, IC Compiler and IC Compiler II place and route solutions, PrimeTime® signoff solution, StarRC extraction, HSPICE®, CustomSim and FineSim® simulation products, Galaxy Custom Designer® schematic, and Laker® layout tools as well as IC Validator physical verification.   

"Long-standing and close collaboration with foundries and end-users of FinFET technology has enabled Synopsys to reach this significant milestone," said Antun Domic, executive vice president and general manager of the Design Group at Synopsys. "Over the past few years, companies have deployed the Galaxy Design Platform for production of semiconductors using FinFET devices. Our customers require the highest performance and lowest power for their designs, which is driving their transition to FinFET. Designers can confidently use Galaxy tools for their FinFET designs and achieve superior quality of results."

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP, and is also a leader in software quality and security testing with its Coverity® solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest quality and security, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.

Editorial Contacts:
Sheryl Gulizia
Synopsys, Inc.
650-584-8635
Email Contact

Lisa Gillette-Martin
MCA, Inc.
650-968-8900 ext. 115
Email Contact

 

 

To view the original version on PR Newswire, visit: http://www.prnewswire.com/news-releases/synopsys-galaxy-design-platform-enables-90-percent-of-volume-production-finfet-designs-300047657.html

SOURCE Synopsys, Inc.

Contact:
Synopsys, Inc.
Web: http://www.synopsys.com




Review Article Be the first to review this article
Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
ICScape: At the Junction of Math & CS, EDA & IP
Peggy AycinenaIP Showcase
by Peggy Aycinena
Arm Momentum: Segars embraces exciting times
More Editorial  
Jobs
REVISED***Director Product Line RF/IC for EDA Careers at San Jose, CA
Senior SW Developer for EDA Careers at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, Germany
Upcoming Events
“Empowering Leadership with WIT and WISDOM” at SEMI 673 South Milpitas Blvd. Milpitas CA - Nov 28, 2017
Artificial Intelligence and Convolution Neural Networks Discussion at San Jose State University Student Union Theater San Jose CA - Dec 4, 2017
Silicon Valley's Only Comprehensive Embedded Systems Conference at San Jose Convention Center 150 W. San Carlos St. San Jose CA - Dec 5 - 7, 2017
Oski Technology’s Decoding Formal Club Meeting at The Conference Center San Jose CA - Dec 7, 2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise