French Institutes IRT Nanoelec and CMP Team up to Offer World’s First Service for Post-process 3D Technologies on Multi-Project-Wafer

  New platform provides access to 3D technologies after regular CMOS MPW runs and  allowsSMEs, research institutes, systems integrators and universities to divide costs

GRENOBLE, France – March 5, 2015 – IRT Nanoelec, an R&D consortium focused on ICT using micro- and nanoelectronics, and CMP, which provides prototyping and low-volume production of ICs and MEMS, are launching a platform for multi-project-wafer, post-process 3D integration (3D-MPW).

The new and disruptive 3D configurations and assemblies created by this IRT Nanoelec/CMP initiative are designed to promote 3D integration.

This service, the first of its kind, extends CMP’s regular MPW offer by using mature 3D post-process technologies at wafer level from IRT Nanoelec. These technologies include through-silicon-vias (TSV, via last), fine-pitch vertical interconnects (micro pillar with solder) and specific finishing for 3D integration like under-bump metallurgy (UBM). These 3D modules will enable a wide panel of new, full 3D architectures, like multiple-die stacking with flip-chip, side-by-side heterogeneous integration, and 3D partitioning of different CMOS dies issued from CMP runs.

3D integration is highly complementary to traditional CMOS scaling, and has very strong potential in terms of size reduction, heterogeneous integration, miniaturization, performance improvements and, possibly, reduction of costs at the system level. The technology is now emerging in more and more applications, such as FPGA, 3D memories and MEM, and involves wafer-level processing on dedicated runs.

The new platform provides for the first time access to post-process 3D technologies after regular CMOS MPW runs, for proof of concept, prototypes and/or small series production. This enables a large group of users to take advantage of cost division made possible, at silicon level, by the MPW regular services followed by post-process technologies. In addition, it allows 3D-MPW users to divide the cost of post processing. This benefits a large group of customers, such as universities, SMEs, research institutes and systems integrators, that usually do not have access to the 3D modules at large foundries.

These 3D post-process technologies require very limited re-design of existing chips, and will be initially used for specific CMOS nodes available at CMP. They may be extended in the future, depending on demand. CMP is responsible for supporting, checking and compiling the customer’s requests, while IRT Nanoelec, which has a very strong background in 3D integration – in particular through the institute CEA-Leti – will manage the 3D post-processing.

More information about this 3D-MPW offer and the 3D technologies from IRT Nanoelec and CMP is available on the websites and

About IRT Nanoelec

Nanoelec Research Technological Institute (IRT), headed by CEA-Leti (, conducts research and development in the field of information and communication technologies (ICT) and, specifically, micro- and nanoelectronics. IRT Nanoelec, working within the framework of programs with investments on future technologies, leverages Grenoble’s proven innovation ecosystem to create the technologies that will power the nanoelectronics of tomorrow, drive new product development and inspire new applications – like the Internet of Things – for existing technologies. The R&D conducted at IRT Nanoelec provides early insight into how emerging technologies such as 3D integration and silicon photonics will affect integrated circuits.

In addition to its R&D activities, IRT Nanoelec runs a technology transfer program set up to ensure that the innovations developed directly benefit businesses — especially small and mid-sized businesses — in all industries. IRT Nanoelec also offers educational and training programs to develop the micro- and nanoelectronics competencies businesses will need to remain competitive in tomorrow’s global markets.

IRT Nanoelec’s unique organization — designed to keep pace with fast-changing markets — offers its partners a more agile model than traditional public-private R&D partnerships.

This work was funded thanks to the French national program: “programme d’Investissements d’Avenir, IRT Nanoelec” ANR-10-AIRT-05. Visit

About CMP

CMP is a service organization in ICs and MEMS for prototyping and low-volume production. Circuits are fabricated for universities, research laboratories and industrial companies. Advanced industrial technologies are available in CMOS, SiGe BiCMOS, HV-CMOS, SOI, P-HEMT GaAs, MEMS, 3D-IC, etc. CMP distributes and supports several CAD software tools for both industrial companies and universities. Since 1981, more than 1,000 Institutions from 70 countries have been served, more than 6,700 projects have been prototyped through 952 runs, and 71 different technologies have been interfaced. For more information, visit:


IRT Nanolec:   Email Contact

CMP:  Email Contact

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