Calypto Design Systems to Showcase Solutions for Low-Power RTL Design and C Based Design & Verification at DVCon 2015

SAN JOSE, Calif. – February 27, 2015 – Calypto® Design Systems, Inc., the leader in low-power RTL design and C-Based design and verification, announced it is demonstrating its Catapult®, PowerPro®, and SLEC® products at DVCon 2015, a three-day exhibit at the Double Tree Hotel in San Jose, CA.  In addition, Calypto key executives will participate in technical and business sessions at the conference.  Used by the world’s leading system and semiconductor companies, Calypto’s family of products enable ASIC, SOC, and FPGA designers of today’s most innovative electronic products to quickly create fully-verified, power-optimized RTL for downstream synthesis and physical design.

WHERE:          DVCon 2015

Double Tree Hotel - 2050 Gateway Pl, San Jose, CA 95110.


Calypto Design Systems


1)     Exhibition

  • WHERE:  Calypto Booth #402.
  • WHEN:     Monday, March 2: 5:00 PM – 7:00 PM

Tuesday, March 3: 2:30PM – 6:00 PM

Wednesday, March 4: 2:30 PM – 6:00 PM

2)     Accellera DVCon Luncheon: What is Needed to Drive Design Efficiency?

  • WHERE: Pine/Cedar room, DoubleTree Hotel, San Jose, CA
  • WHEN:  Monday March 3rd from 12:00 - 1:30PM


3)     Poster Session – “Closing Functional and Structural Coverage on RTL Generated by HLS”

  • WHO: Bryan Bowyer, Sr. Product Marketing Manager
  • WHERE: Gateway Foyer, DoubleTree Hotel, San Jose, CA
  • WHEN: Tuesday March 3rd from10:30 - 11:00AM

Calypto will exhibit and provide demos for its Catapult, PowerPro, and SLEC products.  Catapult High-Level Synthesis products give designers the option to use SystemC or C++ to dramatically shorten the design cycle by producing correct-by-construction, error-free, power optimized RTL. The PowerPro product line enables users to analyze both static and dynamic power usage at the RTL and either automatically or manually create low-power RTL that includes memory and leakage power optimization. The SLEC family of products formally verifies RTL without the need for time consuming simulation and complex testbenches. The end result is a dramatic reduction in time to market and up to 60% reduction in power.

About DVCon:

The DVCon 2015 Expo continues to be the premier conference for design and verification engineers of all levels. It is a unique opportunity for attendees to learn about technology solutions and innovations, identify cutting-edge technologies, and evaluate products side-by-side to help optimize designs and accelerate time-to-market launches. For details and registration visit:

About Calypto:
Calypto® Design Systems is a leading provider of EDA software for high-level synthesis, RTL low power design, and formal verification. Calypto has offices in Europe, India, Japan, Korea, and North America with representation in China, Israel, and Taiwan.

Catapult, Catapult Catware, Calypto, PowerPro and SLEC are registered trademarks of Calypto Design Systems Inc. All other trademarks are property of their respective owners.

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