eInfochips announces eMMC 5.0 Verification IP

Supports eMMC 5.0 from JEDEC, for high performance embedded flash memory systems

Sunnyvale (CA), 5 Feb 2015: eInfochips, a leading Product Engineering Services company has announced the availability of the eMMC 5.0 Verification IP (VIP). Companies designing the next generation embedded flash memory systems can improve the reliability and performance of their products using the eInfochips eMMC 5.0 VIP. The eMMC 5.0 will accelerate RTL verification cycles of JEDEC standards compliant devices for mobiles, tablets and other consumer devices. In line with the Verification IP, eInfochips also offers  ASIC and FPGA verification services for companies in the storage industry.

eInfochips eMMC 5.0 VIP

The  eMMC 5.0 VIP enables design and verification engineers to extensively test the functionality of embedded memory systems. Verification Models and Compliance Test Suites are developed in SystemVerilog (SV) and support UVM environment. The verification architecture includes key modules like the Host Controller and the eMMC device Controller.

The VIP bundles in deliverables like Sample Use Cases, Sanity Test Cases, Verification Environment (to be integrated) and the User Guide.

The eMMC 5.0 VIP is available now to select customers, companies can write to  Email Contact for more information. The complete feature set and specifications data sheet can be found  here.

eInfochips VIP Development and Verification Practice

eInfochips has developed  32 complex VIPs for top global EDA companies and end-customers. Their experience includes VIPs for the latest high-speed and low-power protocol standards, like MIPI, SERDES, USB 3.0, DDR3, HDMI and eMMC. Today, eInfochips has contributed to VIPs that are deployed by hundreds of customers to bring confidence to their ASIC, SOC and FPGA designs.

About eInfochips

eInfochips is a global product innovation partner recognized for technology leadership by Gartner, Frost & Sullivan, NASSCOM and Zinnov. eInfochips has contributed to 500+ products for top global companies, with more than 10 million deployments across the world.

Review Article Be the first to review this article
Downstream : Solutuions for Post processing PCB Designs

Featured Video
Principle Electronic Design Engr for Cypress Semiconductor at San Jose, California
Design Verification Engineer for intersil at Morrisville, North Carolina
Applications Engineer for intersil at Palm Bay, Florida
Upcoming Events
NVIDIA’s GPU Technology Conference (GTC) at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - Mar 26 - 29, 2018
ESC Conference Boston at boston MA - Apr 18 - 19, 2018
IEEE Women in Engineering International Leadership Conference at 150 W San Carlos St San Jose CA - May 21 - 22, 2018
DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: UltraPLL

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise