UMC and Cadence Collaborate to Deliver 28nm Design Reference Flow for ARM Cortex-A7 MPCore-based SoC

· Flow included Cadence Encounter Digital Implementation System, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Quantus QRC Extraction Solution, Physical Verification System, Litho Physical Analyzer and CMP Predictor

SAN JOSE, Calif., Jan. 20, 2015 — (PRNewswire) — Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that United Microelectronics Corporation (NYSE: UMC; TWSE: 2303) ("UMC"), a leading global semiconductor foundry, used Cadence® implementation and signoff tools to produce a silicon-ready 28nm ARM® Cortex®-A7 MPCore-based system on chip (SoC) targeting entry-level smartphones, tablets, high-end wearables and other advanced mobile devices. With the Cadence solution, UMC reduced the time to tapeout by 33 percent versus its previous solution and achieved performance of 1.7GHz. In addition, UMC achieved a dynamic power consumption of less than 200mW, which represents a 20 percent reduction over their previous flow.

Cadence Logo

Using the multi-threaded Encounter® Digital Implementation System, which incorporates GigaOpt route-driven optimization along with CCOpt concurrent clock datapath optimization, resulted in faster turnaround time with significantly improved performance, die area and dynamic power. In addition, the seamless integration of Cadence Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution and Quantus™ QRC Extraction Solution, Physical Verification System, Litho Physical Analyzer and CMP Predictor allowed UMC to perform signoff checks much earlier in the process to affirm that the design functioned as intended upon completion.

"The Cadence massively parallel architecture allowed us to significantly reduce the time spent in signoff analysis, implementation and closure so we could quickly deliver a quality reference design to market that exceeded our power, performance and area expectations," said Shih Chin Lin, senior division director of IP Development and Design Support division  at UMC. "Our mobile customers have very specific device requirements, and we've tested the new chip to ensure that they have a reliable 28nm silicon-ready reference design."

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at

© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and Encounter are registered trademarks and Quantus, Tempus, and Voltus are trademarks of Cadence Design Systems, Inc. in the United States and other countries. ARM and Cortex are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All other trademarks are the property of their respective owners.

For more information, please contact:
Cadence Newsroom
Email Contact

Logo -


To view the original version on PR Newswire, visit:

SOURCE Cadence Design Systems, Inc.

Cadence Design Systems, Inc.

Review Article Be the first to review this article
 True Circuits: IOT PLL


Featured Video
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Principle Electronic Design Engr for Cypress Semiconductor at San Jose, California
Design Verification Engineer for intersil at Morrisville, North Carolina
Upcoming Events
DATE '18: Design, Automation and Test in Europe at International Congress Center Dresden Ostra-Ufer 2 Dresden Germany - Mar 19 - 23, 2018
SemIsrael Technology Week 2018 at Camilo (Green House) Tel Aviv Israel - Mar 19 - 22, 2018
Decoding Formal Club Meeting Featuring Formal Talks by ArterisIP and Cisco at 2099 Gateway Place, Suite 560 San Jose CA - Mar 20, 2018
NVIDIA’s GPU Technology Conference (GTC) at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - Mar 26 - 29, 2018
DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: UltraPLL

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise