New standard will augment existing standards for low-power design and verification methodologies for system-on-chip
SUNNYVALE, Calif. – December 16, 2014 – Real Intent, Inc., whose RTL verification solutions accelerate electronic design sign-off, eliminate complex failures in SoCs, and lead the market in performance, capacity, accuracy and completeness, today announced it has joined the IEEE P2415™ Unified Hardware Abstraction and Layer working group.
The proposed IEEE P2415 “Standard Project for Unified Hardware Abstraction and Layer for Energy Proportional Electronic Systems” is intended to define the syntax and semantics for energy-oriented descriptions of hardware, software and power management for complete electronic systems. It will enable specifying, modeling, verifying, designing, managing, testing and measuring the energy features of an electronic device, covering both the pre- and post-silicon design flow.
Dr. Vinod Viswanath, Sr. Member of Technical Staff at Real Intent and an expert in formal methods for the specification, verification and architecting of low-power hardware systems, is the company’s representative to the Working Group.
“In today’s systems, when SoCs are optimized for some applications, the optimizations are done in isolation without utilizing knowledge of the workloads,” said Dr. Viswanath. “Due to lack of hardware/software cooperation in power management, the platform as a whole cannot anticipate power requirements of the application ahead of time and instead has to perform power management reactively. It is quite clear that neither hardware nor software, in isolation, can make the best decisions about power and performance management, and neither can these be done for the CPU alone, but must now be done at the entire platform level, in a holistic way. Any such holistic approach needs a common representation of power intent at all levels of design hierarchy, and power management engines at each level need to make decisions based on the unified set of power constraints.”
He further explained it is imperative that a holistic platform-level dynamic power management system be aware of different power states supported by different components, both at the architectural and micro-architectural levels; current power consumption of the platform as a whole and at the individual component level; power requirements of applications and their workloads; and continuous feedback from the platform on performance with respect to overall power constraints.
Dr. Viswanath added, “With a synergistic specification of power intent across all of the RT, system, OS, compiler, and application levels, designs will be able to achieve an optimized power solution.”
The new standard, once completed and approved, is intended to be compatible with the current IEEE 1801™-2013 (UPF) standard to support an integrated design flow. In addition, the new standard will complement functional models in standard hardware description languages IEEE 1076™ (VHDL), IEEE 1364™ (Verilog), IEEE 1800™ (SystemVerilog), and IEEE 1666™ (SystemC) by providing an abstraction of the design hierarchy and an abstraction of the design behavior with regard to power and energy usage.
On the hardware side, the standard will describe enumeration of on- and off-chip components, memory map, bus structure, interrupt logic, clock and reset tree, operating states and points, state transitions, and energy and power attributes. On the software side it will describe software activities and events, scenarios, external influences and operational constraints. On the power-management side it will address activity-dependent energy control.
For more information about the IEEE P2415 working group, please visit standards.ieee.org/develop/project/2415.html.
Another working group, P2416, the “Standard Project for Power Modeling to Enable System Level Analysis” is being created to propose a meta-standard focused on parameterization and abstraction, enabling system, software and hardware IP-centric power analysis and optimization. For more information about the IEEE P2416 working group, please visit standards.ieee.org/develop/project/2416.html.
Dr. Vinod Viswanath, Sr. Member of Technical Staff at Real Intent
About Real Intent
Companies worldwide rely on Real Intent’s EDA software to accelerate functional verification and RTL sign-off of electronic designs. The company provides comprehensive CDC verification, advanced RTL analysis and sign-off solutions to eliminate complex failure modes of SoCs. Real Intent’s Meridian and Ascent product families lead the market in performance, capacity, accuracy and completeness. Please visit www.realintent.com for more information.
ASIC: Application-Specific Integrated Circuit
CDC: Clock Domain Crossing
EDA: Electronic Design Automation
IEEE: Institute of Electrical and Electronics Engineers
IP: Intellectual Property
OS: Operating System
RT: Register Transfer
RTL: Register Transfer Level
VHDL VHSIC High-level Design Language
Real Intent and the Real Intent logo are registered trademarks, and Ascent and Meridian are trademarks of Real Intent, Inc. All other trademarks and trade names are the property of their respective owners.
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