HiSilicon Expands Adoption of Cadence Tools and IP for Advanced-Node FinFET Designs

SAN JOSE, Calif., Dec. 1, 2014 — (PRNewswire) — Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that HiSilicon Technologies, a leading provider of communication network and digital media chipset solutions, has signed an agreement to significantly expand its use of the Cadence® digital and custom/analog flows for 16 nanometer FinFET designs, and to collaborate on the design flow for 10 nanometer and 7 nanometer nodes. HiSilicon has also broadly adopted Cadence digital and custom/analog verification solutions, and has licensed Cadence DDR IP and the Cadence 3D-IC solution to deploy multiple heterogeneous dies in a single package on a silicon interposer substrate.

Cadence Logo.

The selection of Cadence tools and IP follows HiSilicon's successful design of the industry's first production 16 nanometer FinFET system-on-chip (SoC). Employing 32 processor cores and a 64-bit architecture, the SoC is a network processor running at speeds up to 2.6 GHz, and was designed using Cadence digital, custom, 3D-IC, verification and emulation tools and DDR4 IP.

For the digital flow, the agreement includes access to Cadence Encounter® Digital Implementation System, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution, and Quantus™ QRC Extraction Solution. For custom/analog design, HiSilicon designers are using Cadence Virtuoso® custom design platform, Spectre® simulation platform, Physical Verification System, Litho Physical Analyzer and CMP Predictor. The agreement also includes an increase in licenses of Incisive® Enterprise Simulator for advanced verification.

For 3D-IC designs, HiSilicon is utilizing the Cadence 3D-IC solution, which includes Encounter Digital Implementation System and Allegro® tools for IC/package co-design, and Voltus and Sigrity solutions for power, thermal and signal integrity verification.

"To continue providing highly differentiated communications and digital media chipset solutions, HiSilicon relies on partners like Cadence to provide implementation and verification solutions that enable high-quality silicon optimized for performance, power and area," said Lin Yu (Colbert), senior director of Platform & Key Technologies Development Department at HiSilicon Technologies. "HiSilicon and Cadence have a long history of close collaboration and ongoing design success. Based on this success we are increasing our use of the Cadence solutions, and look forward to developing innovative new chipset solutions employing 16 nanometer technology, as well as 10 and 7 nanometer nodes in the future."

"Cadence is focused on developing long-lasting partnerships with leading-edge companies like HiSilicon to deliver innovative and groundbreaking devices and systems," said Charlie Huang, executive vice president, Worldwide Field Operations and System & Verification Group at Cadence. "This agreement with HiSilicon builds on years of collaboration, and we look forward to our expanded relationship on new advanced networking solutions."

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at http://www.cadence.com.

© 2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, Allegro, Encounter, Incisive, Spectre, and Virtuoso are registered trademarks and Quantus, Sigrity, Tempus, and Voltus are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

This news release contains certain forward-looking statements, including expectations for product development plans, industry developments, and partner collaborations that are based on our current expectations and involve numerous risks and uncertainties that may cause these forward-looking statements to be inaccurate. Risks that may cause these forward-looking statements to be inaccurate include among others: our product development plans may change, our collaborations with partners may change, or the other risks detailed from time-to-time in our Securities and Exchange Commission filings and reports, including, but not limited to, our most recent quarterly report on Form 10-Q and our annual report on Form 10-K. We do not intend to update the information contained in this press release.

For more information, please contact:
Cadence Newsroom
408-944-7039
Email Contact

Logo - http://photos.prnewswire.com/prnh/20140102/SF39436LOGO

To view the original version on PR Newswire, visit: http://www.prnewswire.com/news-releases/hisilicon-expands-adoption-of-cadence-tools-and-ip-for-advanced-node-finfet-designs-300001983.html

SOURCE Cadence Design Systems, Inc.

Contact:
Cadence Design Systems, Inc.
Web: http://www.cadence.com




Review Article Be the first to review this article

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
H-1B Visa: de Geus’ tragedy looms large
Peggy AycinenaIP Showcase
by Peggy Aycinena
IP for Cars: Lawsuits are like Sandstorms
More Editorial  
Jobs
Mechanical Designer/Engineer for Palo Alto Networks at Santa Clara, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
ASIC/FPGA Design Engineer for Palo Alto Networks at Santa Clara, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
CAD/CAM Regional Account Manager (Pacific Northwest) for Vero Software Inc. at Seattle, WA
Upcoming Events
Embedded Systems Conference ESC Boston 2017 at Boston Convention & Exhibition Center Boston MA - May 3 - 4, 2017
2017 GPU Tech Conference at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - May 8 - 11, 2017
High Speed Digital Design and PCB Layout at 13727 460 Ct SE North Bend WA - May 9 - 11, 2017
Nanotech 2017 Conference & Expo at Gaylord National Hotel & Convention Center WA - May 14 - 17, 2017
DAC2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy