This webinar will take you through the process of adding a digital block to an analog design, starting from RTL behavioral code and proceeding through synthesis, place & route and static timing analysis. We'll be taking a design through our flow, step-by-step, and you will see first-hand the implementation process that you would go through to add a digital block to an existing analog design.
Steve Lin, Senior Application Engineering Manager at Incentia
Steve Lin has over 20 years of experience in digital IC design and EDA industry. He was a design engineer at NEC with extensive experience in timing signoff, physical implementation and verification of MIPS-based micro-processor and digital ASIC designs. Steve moved from design to the EDA industry by joining Cadence. He was involved with technical support of all tools in the digital IC design flow, from RTL to GDSII. Steve, now at Incentia, is responsible for all product offerings in areas of logic synthesis, timing analysis and design closure solutions.
Jeff Miller, Product Manager for Mixed Signal, Tanner EDA
Jeff Miller is a Product Manager at Tanner EDA. He is responsible for Tanner's offerings in the areas of mixed signal design, parasitic extraction, placement and routing automation, and Verilog-AMS simulation. As a Linux/Open Source expert and regular contributor, Jeff was a driving force in expanding Tanner EDA's tool suite to the Linux platform. Prior to joining Tanner, Jeff worked as a Design Engineer on numerous analog, digital, and mixed signal chip development projects for the Defense, medical and commercial markets.
Click the below link to register to attend this webinar.