Live Webinar - Adding a Digital Block to an Analog Design

Live Webinar:
Join us.
Adding a Digital Block to an Analog Design 
Presented by Tanner EDA and Incentia.
Thursday, October 30th at 11:00am Pacific/2:00 pm Eastern.

Abstract

This webinar will take you through the process of adding a digital block to an analog design, starting from RTL behavioral code and proceeding through synthesis, place & route and static timing analysis. We'll be taking a design through our flow, step-by-step, and you will see first-hand the implementation process that you would go through to add a digital block to an existing analog design.

 

Register  

Click the below link to register to attend this webinar.
https://attendee.gotowebinar.com/register/8671827679511233794

Technical Presenter(s): 

Steve Lin, Senior Application Engineering Manager at Incentia 

Steve Lin has over 20 years of experience in digital IC design and EDA industry. He was a design engineer at NEC with extensive experience in timing signoff, physical implementation and verification of MIPS-based micro-processor and digital ASIC designs. Steve moved from design to the EDA industry by joining Cadence. He was involved with technical support of all tools in the digital IC design flow, from RTL to GDSII. Steve, now at Incentia, is responsible for all product offerings in areas of logic synthesis, timing analysis and design closure solutions.

 

Jeff Miller, Product Manager for Mixed Signal, Tanner EDA

Jeff Miller is a Product Manager at Tanner EDA. He is responsible for Tanner's offerings in the areas of mixed signal design, parasitic extraction, placement and routing automation, and Verilog-AMS simulation. As a Linux/Open Source expert and regular contributor, Jeff was a driving force in expanding Tanner EDA's tool suite to the Linux platform. Prior to joining Tanner, Jeff worked as a Design Engineer on numerous analog, digital, and mixed signal chip development projects for the Defense, medical and commercial markets.

Register
Click the below link to register to attend this webinar. 
https://attendee.gotowebinar.com/register/8671827679511233794

  

Request Evaluation License    

Start using Tanner EDA mixed-signal solutions.

Request an evaluation by emailing Email Contact or call +1-626-471-9701.  
http://www.tannereda.com/

Tanner EDA  

 




Review Article Be the first to review this article
 True Circuits: Ultra PLL

Featured Video
Jobs
Principle Electronic Design Engr for Cypress Semiconductor at San Jose, California
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Director, Business Development for Kongsberg Geospatial at remote from home, Any State in the USA
Director, Business Development for Kongsberg Geospatial at Ottawa, Canada
Upcoming Events
IPC Technical Education - PCB Layout - Place and Route at Del Mar Fairgrounds 2260 Jimmy Durante Blvd. Del Mar CA - May 2, 2018
IPC Technical Education at Wisconsin Center 400 W Wisconsin Ave. Milwaukee WI - May 8, 2018
IPC High Reliability Forum at Embassy Suites: Baltimore-At BWI Airport 1300 Concourse Drive Linthicum MD - May 15 - 17, 2018
DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: IoTPLL
DAC2018



Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise