Kodak Alaris Adopts SpyGlass® for FPGA Flow

Enables Complete Validation of CDC Issues Across Design

SAN JOSE, Calif. — (BUSINESS WIRE) — October 20, 2014 — Atrenta Inc., the leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries, today announced that Kodak Alaris has adopted Atrenta's SpyGlass CDC (Clock Domain Crossing) analysis tools to enhance its FPGA design and verification flow. With this technology, Kodak Alaris has realized accuracy and productivity gains for increasingly complex FPGA designs with a growing number of asynchronous clock domains.

“At Kodak Alaris, we specialize in providing innovative imaging products to our customers on a frequent basis,” said Victor Hannak, design and verification engineer, Kodak Alaris. “Productivity is key to meeting our schedules. With SpyGlass advanced CDC checks, we not only meet our schedules for complex designs, but we do it with higher confidence.”

Kodak Alaris realized efficiencies and productivity in analyzing the RTL of their design, without the burden of analyzing the pre-defined IP blocks. They also took advantage of the easy debug across the RTL code, schematics and CDC reports from the SpyGlass platform. This was accomplished by using ‘smart models’ which allow abstraction of secured IP blocks.

With these smart models, SpyGlass CDC enables a seamless flow for designs with embedded IP blocks supplied by FPGA vendors. The models capture key clock-to-pin relationships at the boundary signals of these IP blocks, thus allowing full-chip CDC verification with no loss in accuracy and without having to delve into the internals of the IP. The flow ensures that no CDC issues are introduced as result of incorrect IP integration, especially when some of these blocks are encrypted by the IP vendor. Additional checks from the SpyGlass platform ensure a smoother FPGA implementation.

“Atrenta has become the gold standard for CDC in the industry, and we are excited to extend our solutions to the FPGA design community,” said Piyush Sancheti, vice president of marketing at Atrenta. “Our innovative smart models ensure efficiency for not only billion gate designs, but for embedded 3rd party IP. Solving complex design challenges with innovative techniques continues to be our mission as the industry leader in RTL Signoff.”

About Atrenta Inc.

Atrenta's SpyGlass Predictive Analyzer® significantly improves design efficiency for the world's leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today's consumer electronics revolution. More than two hundred seventy-five companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. And with the addition of BugScope™ verification efficiency is also enhanced, allowing engineers and managers to find the fastest and least expensive path to silicon for complex SoCs.

SpyGlass from Atrenta: Insight. Efficiency. Confidence. www.atrenta.com

© 2014 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo, SpyGlass, SpyGlass Predictive Analyzer, and GenSys are registered trademarks and BugScope is a trademark of Atrenta Inc. All others are the property of their respective holders.

This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this release.



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