DVCon Europe focuses on sharing learnings and best practices in design and verification

Oct 8, 2014 -- With the ever growing complexity of integrated circuits and embedded systems, semiconductor industries are continuously looking for ways to address the design and verification challenges associated to this product integration. In Europe, Intel Mobile Communications, NXP Semiconductors, STMicroelectronics and Infineon Technologies have joined forces to establish a new venue to exchange experiences, knowledge and best practices on design and verification methodologies.

This joined effort resulted in the creation of a brand new conference in Europe, called the Design and Verification Conference & Exhibition. Supported by the Accellera Systems Initiative, DVCon Europe will focus on the application of Electronic Design Automation (EDA) languages, standards and tools. With the emphasis on sharing learnings and best practices in design and verification methods, the DVCon Europe offers a wealth of technical talks and tutorials given by end-users and industry experts.

The first day of DVCon Europe hosts 14 highly technical tutorials, presented by end-users or EDA companies:

  • European SystemC User Group Meeting
  • Advanced Universal Verification Methodology (UVM)
  • An Introduction to using Event-B for Cyber-Physical System Specification and Design
  • Enabling Energy Aware System Level Design with UPF-Based System Level Power Models
  • Virtual Prototyping using SystemC TLM-2.0
  • Requirements-driven Verification Methodology for Standards Compliance
  • Easier UVM – Making Verification Methodology more Productive
  • The How To’s of Metric Driven Verification to Maximize Verification Productivity
  • Creating Portable Tests with a Graph-Based Test Specification
  • Attack Your SoC Power Challenges with Virtual Prototyping
  • Algorithm Verification with Open Source and SystemVerilog
  • Revolutionary Debug Techniques to Improve Verification Productivity
  • Architecting your UVM Testbench for Simulation/ Acceleration Reuse to enable Block to System Verification Productivity
  • Extending Proven Digital Verification Techniques for Mixed-Signal SoCs with VCS AMS

On the second day of DVCon Europe, the conference program starts with a keynote of Bernd Adler, Wireless CTO and Division Vice President of Intel Mobile Communications, entitled “Tomorrow’s Smart Mobile Systems - by the Power of Ten”. The technical program that follows covers presentations and a poster session in the following areas:

  • Analog/Mixed-Signal Design and Verification
  • Advanced Verification
  • IP Reuse & Design Automation
  • System Level Design & Verification
  • Low Power Methodologies
  • Verification Management

DVCon Europe also hosts an exhibition, where EDA tool companies, training institutes and service providers give demonstrations of their products and solutions. A unique occasion of having many companies active in design and verification under one roof!

Registration is still open for DVCon Europe: visit www.dvcon-europe.org for more information.

Martin Barnasconi

DVCon Europe General Chair

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