New ARM Implementation Solutions Reduce Time to Market for FinFET Designs

SANTA CLARA, Calif. — (BUSINESS WIRE) — October 1, 2014 — ARM® today announced the introduction of two new physical IP implementation solutions for its silicon partners to help simplify the path to implementation for their FinFET physical designs. ARM Artisan® Power Grid Architect will reduce overall design time by creating optimal SoC power grid layouts while ARM Artisan Signoff Architect increases accuracy and precision in managing on-chip variation over existing methodologies.

These new physical IP implementation solutions strengthen the commitment from ARM to enable delivery of real silicon with the speed consumers are demanding. Artisan Power Grid Architect creates power-optimized networks and removes the need for implementation teams to apply detailed FinFET design rules, allowing extra time to explore power network options for a particular design. Additionally, Artisan Power Grid Architect automates critical aspects of floorplanning to improve overall power, performance and area (PPA), especially for power grid design. Artisan Signoff Architect adds enhancements and more precision to stage-based on-chip variation (SB-OCV) signoff methodologies, adding accuracy that is not supported in the existing IP model format.

“ARM Physical IP for TSMC 16nmFinFET process technology ensures the availability of leading-edge design solutions for ARM-based SoCs,” said Ron Moore, vice president of marketing, physical design group, ARM. “Artisan Power Grid Architect and Artisan Signoff Architect help to improve power, performance and area and provide a new level of signoff accuracy and reduced time-to-market for TSMC’s FinFET process. These new implementation solutions underscore our commitment to innovation for our silicon partners.”

Artisan Power Grid Architect and Artisan Signoff Architect are used exclusively with ARM Artisan advanced physical IP for TSMC 16nm FinFET (CLN16FF+). The beta release of Artisan Power Grid Architect for TSMC CLN16FF+ will be available October 2014, while Artisan Signoff Architect will be available for TSMC CLN16FF+ beta release in Q4 2014.

Ends

About ARM

ARM is at the heart of the world's most advanced digital products. Our technology enables the creation of new markets and transformation of industries and society. We design scalable, energy efficient-processors and related technologies to deliver the intelligence in applications ranging from sensors to servers, including smartphones, tablets, enterprise infrastructure and the Internet of Things.

Our innovative technology is licensed by ARM Partners who have shipped more than 50 billion System on Chip (SoCs) containing our intellectual property since the company began in 1990. Together with our Connected Community, we are breaking down barriers to innovation for developers, designers and engineers, ensuring a fast, reliable route to market for leading electronics companies. Learn more and join the conversation at http://community.arm.com.

ARM and Artisan are registered trademarks of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved. All other brands or product names are the property of their respective holders. "ARM" refers to ARM Holdings plc (LSE: ARM and NASDAQ: ARMH) and members of its corporate group as constituted from time to time.

None of the information contained in this document may be adapted, republished, or reproduced in any form except with the prior written permission of the copyright holder, but links may be posted directly to this document from other websites, and the whole of the document correctly attributed and unmodified may be shared freely, unless the copyright holder at any time withdraws these permissions. This document is intended only to provide information to the reader about the relevant product(s) described or mentioned. All information is provided "as is" and without warranty. ARM makes no representation as to the product(s), and ARM shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information.



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