MIPI Alliance Introduces MIPI C-PHY™ Specification and Updates its D-PHY™ and M-PHY® Specifications

The New Releases Expand the MIPI Alliance’s Family of Physical Layer Specifications for Mobile and Mobile-Influenced Applications

PISCATAWAY, N.J. — (BUSINESS WIRE) — September 17, 2014 — The MIPI® Alliance, an international organization that develops interface specifications for mobile and mobile-influenced industries, today introduced its new MIPI C-PHY™ specification, a physical layer interface for camera and display applications. The specification expands the MIPI Alliance’s family of physical layer specifications, broadening the variety of interface choices available to manufacturers and opening up new opportunities for companies to differentiate their product designs based on business-specific strategies or technology requirements.

“We are very pleased to add MIPI C-PHY to our widely adopted family of physical layer technologies,” said Joel Huloux, chairman of the board of MIPI Alliance. “The MIPI Alliance is all about helping companies interconnect components to create successful mobile designs and as an organization we provide a selection of physical layer technologies to support a full range of application requirements. Companies developing new products can now select from MIPI C-PHY as well as our newly updated MIPI D-PHY specification and MIPI M-PHY® specification and apply the specifications to best meet their needs.”

MIPI C-PHY, released as v1.0, is designed to connect camera and display modules to an application processor. The interface allows system designers to easily scale the existing MIPI Alliance Camera Serial Interface (CSI-2) and Display Interface (MIPI DSI) ecosystems to support higher resolution image sensors and displays while at the same time keeping power consumption low. It also supports soft configurability of lanes within a link to optimize bandwidth and minimize pin count. MIPI C-PHY can be implemented with MIPI D-PHY on the same device pins, which allows connections to the companion device with either PHY technology.

“The MIPI C-PHY specification was developed to reduce the interface signaling rate to enable a wide range of high-performance and cost-optimized applications, such as very low-cost, low-resolution image sensors; sensors offering up to 60 megapixels; and even 4K display panels,” said Rick Wietfeldt, chair of the MIPI Alliance Technical Steering Group.

MIPI C-PHY accomplishes this by departing from the conventional differential signaling technique on two-wire lanes and introducing 3-phase symbol encoding of about 2.28 bits per symbol to transmit data symbols on 3-wire lanes, or “trios” where each trio includes an embedded clock. Three trios operating at the MIPI C-PHY v1.0 rate of 2.5 Gsym/s achieve a peak bandwidth of 2.5 Gsym/s times 2.28 bits/symbol, or about 17.1 Gbps over a 9-wire interface that can be shared, if desired, with the MIPI D-PHY interface.

The MIPI Alliance is also pleased to announce the continued development, support and forward progress of its PHY family with updates to the MIPI D-PHY and MIPI M-PHY physical layer technologies. The updated MIPI D-PHY specification, v1.2, introduces lane-based data skew control in the receiver to achieve a peak transmission rate of 2.5 Gbps/lane or 10 Gbps over 4 lanes, compared to the v1.1 peak transmission rate of 1.5 Gbps/lane or 6 Gbps over 4 lanes. The MIPI M-PHY v3.1 specification introduces transmitter equalization to improve support for challenging channels while maintaining the peak transmission rate of 5.8 Gbps/lane or 23.2 Gbps over 4 lanes, which was achieved in its v3.0 specification.

“The MIPI Alliance’s three physical layers, combined with MIPI Alliance application protocols, address the evolving interface needs of the entire mobile device. Fundamentally, MIPI Alliance interfaces enable manufacturers to simplify the design process, reduce costs, create economies of scale and shorten time-to-market,” said Ken Drottar, chair of the MIPI Alliance PHY Working Group.

The MIPI Alliance’s family of specialized physical layers supports a variety of mobile device protocols for chip-to-chip, camera and display applications that require high-performance, low-power serial interfaces and produce very low electromagnetic interference (EMI). Each of the physical layers offers unique advantages and features that collectively address the most essential functions needed in today’s smartphones, tablets and laptop computers. MIPI M-PHY, for example, provides a high-speed physical layer specification for data transmission in a mobile terminal, and MIPI D-PHY is widely used for camera and display applications.

The MIPI Alliance makes its PHYs and protocols available as individual interfaces, enabling companies to adopt those that meet their particular design needs. Because mobile connectivity is increasingly finding its way into additional industries, the MIPI Alliance works cooperatively with other standards development organizations whose technologies can use or benefit from MIPI interfaces. For example, MIPI M-PHY has been adopted as the physical layer technology enabling popular PC protocols to operate in mobile terminals. Some of these externally developed standards include Universal Flash Storage (UFS) from the JEDEC® Solid State Technology Association; Mobile PCI Express (M-PCIe®) from the PCI-SIG®, and SuperSpeed USB Inter Chip (SSIC) from the USB 3.0 Promoters Group.

MIPI C-PHY v1.0, MIPI D-PHY v1.2 and MIPI M-PHY v3.1 are readily available to MIPI Alliance members and can be downloaded from the member portal on the MIPI Alliance web site.

For more information about MIPI Alliance’s physical layer specifications, please visit http://bit.ly/MIPIPHYSpecs .

1 | 2  Next Page »

Review Article Be the first to review this article
Aldec Webinar Nov 30

Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Computer History Museum: the Future of War is Here
More Editorial  
ASIC Design Engineer for Infinera Corp at Sunnyvale, CA
Senior PIC Test Development Engineer for Infinera Corp at Sunnyvale, CA
Principal PIC Hardware Controls Engineer for Infinera Corp at Sunnyvale, CA
Senior SW Developer for EDA Careers at San Jose, CA
REVISED***Director Product Line RF/IC for EDA Careers at San Jose, CA
Upcoming Events
“Empowering Leadership with WIT and WISDOM” at SEMI 673 South Milpitas Blvd. Milpitas CA - Nov 28, 2017
Artificial Intelligence and Convolution Neural Networks Discussion at San Jose State University Student Union Theater San Jose CA - Dec 4, 2017
Silicon Valley's Only Comprehensive Embedded Systems Conference at San Jose Convention Center 150 W. San Carlos St. San Jose CA - Dec 5 - 7, 2017
Oski Technology’s Decoding Formal Club Meeting at The Conference Center San Jose CA - Dec 7, 2017
TrueCircuits: IoTPLL

Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise