DVCon Europe program highlights EDA standards adoption, developments and innovation

Sep 5, 2014 -- With the first edition of the Design and Verification Conference & Exhibition in Europe ahead of us, we are excited to announce a fantastic technical program! Similar to the well-known DVCon event in the United States, the European edition is centered on the application of EDA standards, languages and tools for the design and verification of electronic systems and integrated circuits.

DVCon Europe is driven by European Semiconductor companies, such as NXP, STMicroelectronics, Intel Mobile Communications and Infineon, with great support of the Accellera Systems Initiative. This will make DVCon Europe a highly industry-focused event, with a clear technical focus on standards for system-level design, verification and validation, IP reuse, analog/mixed-signal verification and low power design methods. This resulted in a Technical Program with the following highlights:

  • Industry Keynote Speaker: Bernd Adler from Intel Mobile Communications, Germany
  • 14 tutorials moderated by user companies, tool providers and training partners
  • More than 25 technical paper presentations
  • Poster session hosting more than 15 posters
  • Exhibition show with demos from training partners, design tool and IP service providers
  • DVConnect Networking Reception – Get connected with the experts

When looking at the program content, we see stories around the adoption of SystemC Transaction-Level Modeling (TLM), Universal Verification Methodology (UVM) and IP-XACT standards. Interesting developments are presented around the IEEE1801 Unified Power Format (UPF) standard to support system-level power modeling and the use of analog/mixed-signal language, also in combination with UVM. The program also reveals some unique innovations, such as the introduction of a new verification language called ‘Vlang’ and the creation of UVM in SystemC named ‘UVM-SystemC’. As such, the DVCon Europe program offers a wealth of interesting technical topics for design and verification engineers of all experience levels.

DVCon Europe also hosts a vendor exhibition. On Tuesday and Wednesday you can meet with EDA tool companies, training institutes and service providers to get in-depth demonstrations of their products, solutions and services. Benefit from this unique occasion of having all important companies active in design and verification under one roof! We will offer a venue where verification engineers, system and IC architects, IP integrators, EDA tool companies and service providers can meet and share their experience. 

I am sure you will learn many things at DVCon Europe – and things you can immediate use in your daily professional work. Early registration for DVCon Europe is still possible until September 12. I encourage you to register early, as space and seating is limited.

I am looking forward to meeting you on October 14 and 15 in Munich, Germany.

Martin Barnasconi
DVCon Europe General Chair

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