STATS ChipPAC’s fcCuBE Technology Surpasses 100 Million Unit Milestone

Singapore 20 August 2014 – STATS ChipPAC, a leading provider of advanced semiconductor packaging and test services, announced today that it has shipped over 100 million semiconductor packages with the Company’s fcCuBE® technology, advanced flip chip packaging with fine pitch copper (Cu) column bumps, Bond-on-Lead (BOL) interconnection and enhanced assembly processes.

fcCuBE® technology is well established in the mobile market with the most significant production volume to date in small chip scale packages where the performance, size and cost benefits successfully address customer requirements in smartphones, tablets and wearable devices. The compelling performance and cost advantages of fcCuBE are also accelerating the diversification of this advanced technology into large die packages for consumer and networking applications where very high performance, reliability and processing speeds are imperative.

“The exceptional success of fcCuBE in the mobile market over the last year is a reflection of the complex performance and form factor requirements that our customers face and the clear advantages of this advanced technology. Demand for greater functionality and significantly higher processing speeds in consumer and networking devices is also driving flip chip packaging technology for ICs containing ultra low K dielectrics, very large package sizes, very fine bump pitches and lead-free solder,” said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC. “fcCuBE has proven to be a scalable technology that cost effectively addresses the technical requirements for high performance devices.”

In consumer applications such as set top boxes (STB) and digital television (DTV) ICs, higher functionality, faster data rates and increased bandwidth are required for enhanced user interfaces, rich graphics and outstanding audio quality. Wire bonding technology, a popular packaging choice in the past, is often unable to successfully address the increased thermal and electrical performance requirements for next generation consumer applications and, as a result, semiconductor companies are turning to high performance flip chip interconnect to differentiate their products. The BOL interconnection and very fine pitch Cu bumps in fcCuBE technology deliver exceptionally high I/O density and bandwidth with excellent electromigration (EM) performance for high current carrying applications such as STB and DTV ICs at a cost competitive price point for customers.

The functional and performance requirements for networking devices continue to evolve as well, driving demand for larger and thinner packages supporting very high current densities and bandwidth requirements. These high performance devices also require a steady and consistent supply of power which becomes challenging as device functionality increases. In addition, there are yield and reliability concerns that arise from the larger package sizes and very fine pitch interconnection that is required to produce higher I/O densities.  fcCuBE technology significantly reduces the substrate layer count and complexity, achieving a thinner, lower cost package with high power integrity, superior control over thermal performance and higher resistance to EM over standard flip chip packages.

“Over the course of the last year, rapidly increasing density, performance and bandwidth challenges have become a driving force for customers who are looking for a powerful, cost effective flip chip technology to support their next generation mobile, consumer and networking applications,” said Chong Khin Mien, Senior Vice President of Product and Technology Marketing, STATS ChipPAC. “The growth in our fcCuBE production volume is a clear vote of customer confidence in our ability to deliver an advanced packaging solution that best meets the cost and performance targets for their specific product requirements.”



Read the complete story ...


Review Article Be the first to review this article
Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Job Openings: Can EDA Predict the Future
More Editorial  
Jobs
ASIC Design Engineer 2 for Ambarella at Santa Clara, CA
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
Test Development Engineer(Job Number: 17001697) for Global Foundaries at Santa Clara, CA
Engr, Elec Des 2 for KLA-Tencor at Milpitas, CA
Verification Engineer for Ambarella at Santa Clara, CA
Timing Design Engineer(Job Number: 17001757) for Global Foundaries at Santa Clara, CA
Upcoming Events
CDNLive Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Apr 11 - 12, 2017
10th Anniversary of Cyber-Physical Systems Week at Pittsburgh, PA, USA PA - Apr 18 - 21, 2017
DVCon 2017 China, April 19, 2017, Parkyard Hotel Shanghai, China at Parkyard Hotel Shanghai Shanghai China - Apr 19, 2017
Zuken Innovation World 2017 at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
S2C: FPGA Base prototyping- Download white paper



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy