Cadence Achieves PCIe 3.0 Compliance for PHY and Controller IP

SAN JOSE, Calif., July 29, 2014 — (PRNewswire) —  Cadence Design Systems, Inc., a leader in global electronic design innovation, today announced that its PHY IP and Controller IP for PCI Express® (PCIe®) 3.0 have passed certification tests from PCI-SIG®. The solutions were tested to their full potential and complied with the full speed of 8GT/s for PCIe 3.0 technology. The compliance assures designers that their system-on-chip (SoC) designs will operate as expected.

Cadence Logo.

"As a PCI-SIG member for more than 10 years, Cadence holds a valued role in the success of PCIe technology," said Al Yanes, president and chairman of PCI-SIG. "By participating in the compliance program, Cadence is helping to ensure the continued adoption of the PCIe architecture."

The Cadence PHY IP for PCIe 3.0 technology is a low power solution, enabling customers to implement a PCIe 3.0x16 solution with power consumption under 1W. It also enables seamless SoC integration by allowing customers to prototype their design and test compatibility with other PCIe devices. The unique FPGA platform for evaluation and product development offered with the solution supports the 8GT/s data rate specified under PCIe 3.0 requirements.

"With the lowest power consumption in the market, our certified solution enables customers to build extremely power-efficient designs," said Gary Dick, PCIe architect, IP Group at Cadence. "With the FPGA platform, our customers can fully test and emulate application logic before the design is implemented."

"As part of its successful PCIe compliance testing, Cadence utilized the leading-edge PCIe 3.0 test and development tools from Teledyne LeCroy," said John Wiedemeier, product marketing manager at Teledyne LeCroy. "This is the latest example of many years of partnership between the two companies on comprehensive compliance testing that enable designers to confidently integrate high-speed PCIe interfaces into their SoCs."

Cadence's PHY IP and its Controller IP for PCIe 3.0 architecture are offered as an integrated solution. When tested using the industry-leading Cadence verification IP (VIP) for PCIe technology, it can save customers months of integration and verification work.

For more information on Cadence IP for PCIe offerings, please visit:
http://ip.cadence.com/knowledgecenter/customize-main/pcie-resources

About Cadence

Cadence (NASDAQ: CDNS) enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.

About PCI-SIG

PCI-SIG is the consortium that owns and manages PCI specifications as open industry specifications. The organization defines I/O (input/output) specifications consistent with the needs of its members. Currently, PCI-SIG is comprised of nearly 800 industry-leading member companies. To join PCI-SIG, and for a list of the Board of Directors, visit  www.pcisig.com.

© 2014 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries.  All other trademarks are the property of their respective owners.

PCI-SIG, PCI Express, PCIe and M-PCIe are trademarks or registered trademarks of PCI-SIG. 

For more information, please contact:
Cadence Newsroom
408-944-7039
Email Contact

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SOURCE Cadence Design Systems, Inc.

Contact:
Cadence Design Systems, Inc.
Web: http://www.cadence.com




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