SUNNYVALE, Calif. – July 22, 2014 – Real Intent, Inc., a leading provider of EDA software products today announced a new version of its Ascent Implied Intent Verification (IIV) tool for static functional analysis of digital IC designs, delivering new debug enhancements for users. Ascent products find elusive bugs and eliminate sources of uncertainty that are difficult to uncover using traditional Verilog or VHDL simulation, leading to both improved QoR and productivity of design teams.
New Ascent IIV features and enhancements include:
- Specialized report categories for FSMs, language checks, design checks, coverage, and X-verification with control of report depth for easier debug review
- Causality reporting, which shows the secondary errors caused by each primary error so designers can rank the impact of fixing primary errors
- New language checks for violations of SystemVerilog constructs – unique, priority, and enumeration
- Easier setup for quick adoption
- 15 other analysis and debug improvements
Lisa Piper, senior manager of technical marketing at Real Intent, said, “IIV’s root cause analysis dramatically reduces debug time by focusing the effort on the real design problems, without the distraction of related secondary issues. Our new specialized reports make it easier for designers to focus on categories of concern, tailor the results, and see the impact of fixing primary errors. For the first time, IIV now has checks for SystemVerilog constructs that are not in classic Verilog code. Our Ascent products remain the fastest and highest-capacity static verification solutions available for uncovering issues prior to digital simulation.”
To see a video interview of Lisa Piper discussing the new release of IIV and trends in automatic verification, please visit http://youtu.be/Pn3w-vzt8IU.
The latest release of Ascent IIV will be available on July 28 for download from the Real Intent web-site.
About Ascent IIV
Ascent IIV is a state-of-the-art automatic RTL verification tool. It finds bugs using an intelligent hierarchical analysis of design intent. No test bench or assertions are required, making it easy and efficient to find RTL bugs earlier in the design flow before they become more expensive to uncover. The analysis minimizes debug time by identifying the root cause of issues, and provides the VCD traces that show the sequence of events leading to an undesired state. Ascent IIV has the speed and capacity to handle design blocks exceeding 250K gates and provides a wide variety of complex checks including FSM deadlocks, bus issues, and constant bits and nets. If SVA or VHDL assertions written in PSL are available, Ascent IIV can use these as constraints to enhance the analysis. Please click here for a recent announcement about how Real Intent’s Ascent IIV software accelerates design debug for a customer.
About Real Intent
Companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and advanced sign-off of electronic designs. The company provides comprehensive CDC verification, advanced RTL analysis and sign-off solutions to eliminate complex failure modes of SoCs. Real Intent’s Meridian and Ascent product families lead the market in performance, capacity, accuracy and completeness. Please visit www.realintent.com for more information.
CDC: Clock Domain Crossing
EDA: Electronic Design Automation
FSM: Finite-State Machine
IC: Integrated Circuit
PSL: Property Specification Language
QoR: Quality of Results
RTL: Register Transfer Level
SVA: SystemVerilog Assertions
VCD: Value Change Dump
VHDL: Very High-level Design Language
Real Intent and the Real Intent logo are registered trademarks, and Ascent and Meridian are trademarks of Real Intent. All other trademarks and trade names are the property of their respective owners.
Sarah Miller for Real Intent
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