Board test and debug security via JTAG, IJTAG is explored in new eBook

Richardson, TX (July 1, 2014) – Visibility into the operations and data stored on circuit boards and in semiconductors is the goal of test and debug. Unfortunately, this is often at odds with the goals of circuit board security. A new eBook published by ASSET® InterTech ( www.asset-intertech.com) addresses the inherent weaknesses in the IEEE 1149.1 Boundary-Scan (JTAG) standard’s Test Access Port (TAP) found on many circuit boards and chips, and describes several general security strategies based on the IEEE 1687 Internal JTAG (IJTAG) standard that can overcome these problems.

“There is no industry standard for making a circuit board’s test and debug facilities secure,” said Al Crouch, chief technologist, embedded instrumentation methodologies and IJTAG, for ASSET and one of the co-authors of the eBook. “As a result, any board test security is usually derived from the security contained in the chips on a board and each chip has its own security methods. Board-level operations may have some encryption for security purposes, but the TAP still represents a vulnerability that hackers and counterfeiters can exploit unless security measures are designed into the circuit board.”

Titled “JTAG | IJTAG Semiconductor and Board Test Security”, the new eBook is available for free. It can be downloaded from the eResources center on the ASSET website at: http://www.asset-intertech.com/Products/Boundary-Scan-Test/BST-Software/JTAG-IJTAG-Semiconductor-and-Board-Test-Security

Other informative eBooks, white papers and videos on issues relating to chip, board and system debug, validation and test can be downloaded from the ASSET website at: http://www.asset-intertech.com/eResources

About ASSET InterTech

ASSET InterTech is a leading supplier to the electronics industry of tools based on embedded instrumentation. Its SourcePoint debugger and the ScanWorks platform for embedded instruments overcome the limitations of external test and measurement equipment by applying instrumentation embedded in code and semiconductors to debug and validate software and firmware, and to perform design validation and manufacturing test on chips and circuit boards. ASSET’s recent acquisition of Arium ( www.arium.com) added a powerful suite of firmware debug and trace tools to the ScanWorks platform. Designers can quickly debug firmware and then diagnose how it interacts with hardware. ASSET InterTech is located at 2201 North Central Expressway, Suite 105, Richardson, TX 75080.

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