IROC to showcase TFIT and SOCFIT tools at DAC (San Francisco) Allowing Designers to Analyze and Prevent Soft Errors before Silicon

TFIT and SOCFIT enables to perform Soft Error System Analysis, ASIC Analysis and Cell SER predictions on a regular basis

DAC Conference, San Francisco, CA – June 1st, 2014 -- IROC Technologies® developer of the industry standard for integrated circuit (IC) soft error analysis and prevention, will showcase TFIT®  and SOCFIT® at the 51st Design Automation Conference (DAC)  at the Moscone Center in San Francisco, CA from June 2nd   to 4th. The company will be presenting the latest functionalities and performances of TFIT, with the latest process nodes models from the top two foundries in the world which have chosen IROC as their soft error rate (SER) partner for test and simulation at the booth # 817. The TFIT solution focuses at cell level on the impact of natural radiation effects called Soft Error on the reliability of integrated circuits (ICs). TFIT enables design engineers to be proactive in assessing soft error performance before tape-out an optimizing cell design to improve its performance, especially at 65nm and below. The need for Soft Error assessment has been increasing in the past years, reaching a point at 28nm and beyond where many designers have to use an accurate tool to perform this task.

The SOCFIT platform is a prediction and analysis tool that links raw cell soft error rate (SER)  from TFIT or test to circuit SER and system SER.  SOCFIT  allows chip architects to predict the FIT rate (Failure In Time) early in the design (RTL, gate netlist), budget mitigation strategies to reach the FIT goal, analyze quickly the effects of derating or masking, optimize the mitigation, and report the FIT rate to their customers with solid technical evidences.

Soft errors are caused by interactions of natural radiation with silicon. They can happen at any time and at any location during the operational life of the device. The smaller the technology, the higher the sensitivity of whole designs to soft errors is, and this effect cannot be eliminated using classic post-manufacturing reliability techniques like burn-in or stress test. Typically expressed as the number of failures in time (FIT), the SER per IC is growing as geometries shrink and now impacts many fabless companies and independent device manufacturers (IDMs). FIT rates have been traditionally measured post silicon by radiation testing. TFIT and SOCFIT now allows accurate predictions very early in the design phase.

IROC has been in the soft error business for fourteen years, developing simulation expertise and tools while also providing test and analysis services and helping dozens of customers among the largest semiconductor companies. TFIT predicts the SER FIT of any CMOS digital cell. The company’s novel algorithms capture the complexity of cosmic rays interactions with silicon dies very quickly and accurately, using the cell SPICE netlist and layout as design input, the transistor model and process response model provided by the foundries as technology input. TFIT is also complementary to IROC’s circuit level SER assessment tool ( SOCFIT) and is used to build a database of FIT rates for each individual cell used in a circuit. SOCFIT is modular and powerful derating analysis tool, assessing and simulating the propagation of current glitches from the gate hit by the particle, through the circuitry all the way to the functional output of the circuit. In many cases, the current glitch does not propagate and can be discarded. This is the concept of derating which SOCFIT analyzes in details from the RTL or Gate Netlist of the device.

 “Both TFIT and SOCFIT tools have been designed to allow analysis by non-specialists of  very complex phenomena like nuclear interactions within devices and the propagation of their effects to large designs,” said Olivier Lauzeral, general manager for IROC Technologies Corp.   “Our decade of experience with soft error testing and analysis and hundreds of cases analyzed for many companies made our tools output accurate, yet very fast and easy to use.”


Both tools are offered either as time based floating licenses, or as design services where the tool is run by IROC engineers on customer cases.

TFIT process models available to date range from 180nm to FinFET, covering almost every node in between. Additional models will be introduced throughout the year, available either at IROC (generic models) or through specific foundries.

About IROC

IROC Technologies significantly lowers the risk of radiation-induced failures for integrated circuits (ICs) in the field, throughout a product’s lifetime, by optimizing the design. The company provides chip designers with soft error analysis software, test services and expert advisors and auditing to improve IC reliability and quality.  TFIT and SOCFIT are used by companies that need high performance and high reliability in application areas such as cloud infrastructure, Internet infrastructure, automotive, medical devices and the military/ aerospace industry. IROC’s U.S. headquarters are in Silicon Valley, California, and its European headquarters are in Grenoble, France.

IROC Technologies is a registered trademark and TFIT and SOCFIT are trademarks of IROC Technologies Corporation. All other trademarks are the property of their respective owners. 

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Media Contacts:

Olivier Lauzeral
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