WinterLogic Announces Inspect Fault Analysis Tool

Roseville, MN, May 22, 2014 -- WinterLogic, Inc., the industry leader in fault simulation solutions, today announced the release of Z01X 2.8 with Inspect, a graphic interface tool designed for exploring the quality of a design’s test coverage. Leveraging over twenty years of experience in fault simulation technology, Inspect combines a flexible suite of analysis tools with Z01X’s powerful fault simulation platform to provide an advanced environment for investigating fault coverage.

“As designs continue to increase in complexity, debug and analysis tools like Inspect represent our continued commitment to advancing fault simulation technology,” states Jason Campbell, WinterLogic’s President. “Inspect’s linked viewers for source code, hierarchies and fault definitions enable quick identification of poorly tested areas in complex designs.”

“We are really excited about this new capability. Our customers who perform extensive RTL or gate-level fault simulation now have a unique platform to efficiently develop better test vectors. Visualization of faults in the context of surrounding logic provides useful feedback for functional, BIST and diagnostic patterns,” says Olivier Bolon, Winterlogic’s director of Sales and Business Development.

WinterLogic’s Z01X is the only commercial fault simulator with the capacity and performance to successfully run the largest SoC for wireless, graphics and computing. With its advanced feature set, WinterLogic’s Z01X is the tool of choice for meeting the most stringent automotive manufacturing and safety standards such as AEC-Q100 and ISO26262. Z01X 2.8 adds not only the Inspect fault analysis tool, but also continued enhancements to SystemVerilog support, 2X RTL simulation performance improvements, and a new TCL scripting interface.

About WinterLogic
WinterLogic provides fault simulation products that analyze a test suite’s ability to detect manufacturing defects and design errors. Z01X for Manufacturing Assurance helps companies hit their zero-defect manufacturing target and reduce testing costs by selecting the most effective tests and closing the ATPG coverage gap. Z01X for Verification Assurance uses functional fault simulation to quickly identify untested areas in RTL designs and weaknesses in verification test suites. 

Contact: 
Jason Campbell
WinterLogic, Inc.
651-633-4645
Email Contact

 




Review Article Be the first to review this article
Aldec

Downstream : Solutuions for Post processing PCB Designs

Featured Video
Jobs
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Principle Electronic Design Engr for Cypress Semiconductor at San Jose, California
Director, Business Development for Kongsberg Geospatial at remote from home, Any State in the USA
Director, Business Development for Kongsberg Geospatial at Ottawa, Canada
Upcoming Events
IPC Technical Education - PCB Layout - Place and Route at Del Mar Fairgrounds 2260 Jimmy Durante Blvd. Del Mar CA - May 2, 2018
IPC Technical Education at Wisconsin Center 400 W Wisconsin Ave. Milwaukee WI - May 8, 2018
IPC High Reliability Forum at Embassy Suites: Baltimore-At BWI Airport 1300 Concourse Drive Linthicum MD - May 15 - 17, 2018
DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: IoTPLL
DAC2018



Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise