Jivaro netlist reduction improves simulation performance up to 10x while preserving accuracy for 28nm and below
May 27, 2014 - San Francisco, CA and Grenoble, France -- Backend verification specialist EdXact SA today announced the availability of new critical capabilities for its complete family of products, Jivaro, Belledonne and Viso. EDXACT will showcase the latest features of the software tools that help design and verify advanced layouts impacted by parasitic effects.
Flagship product Jivaro provides mathematics-based netlist reduction for netlists with parasitics in order to speed up all Spice simulators. Early adopters have recently reported a speed up of netlist simulation in sub-20nm processes by 6x to 10x. In other cases, 80 minutes of Jivaro resulted in a savings of 24 hours of simulation time. Or yet another case: 50 minutes of Jivaro reduced the overall simulation time by two full days. Best of all, Jivaro can be applied without changing the existing tooling. Some of the novelties in Jivaro include:
- Reduction of resistors with temperature coefficients
- Reduction of resistors with models
- Reduction of negative resistors. Modern design kits use negative resistors, which turn simple reduction schemes useless
- Additional reduction of active devices
For some analyses, Spice simulation can be replaced by a more intelligent, much faster and dedicated analysis. EDXACT proposes two tools in this area; Belledonne and Viso. These have been extended with new features for the most advanced processes.
Belledonne is positioned after layout extraction, so there is no need to change the existing extraction tool. Belledonne compares two extracted netlists with respect to the parasitics (R, C) and their impact on timing (RC delay). It can handle very large files and is suitable for batch processing.
Viso analyzes layouts. Just like Belledonne, it is positioned after layout extraction and does not force the user to characterize a new layout extraction tool. Instead, it adds a lot of insight into the extracted netlists. And it is very fast delivering Spice accuracy at a fraction of the usual run times. Users of Viso report that they use the tool to:
- Detect design issues that passed DRC/LVS such as open connections, dangling sections and excessive path resistance
- Calculate different metrics on the nets, like effective resistance point-2-point or point-2-many, total capacitance, effective RC delay and other statistics
- Determine the contribution of each metal layer to the resistance or RC delay
- Determine PowerMOS key characteristics like ON-resistance, input and output capacitances, including a verification step of reliability constraints
- Verify differential pair routing
About DAC 2014
The Design Automation Conference 2014 is being held in San Francisco, June 2-4 at the Moscone Convention Center. EdXact can be visited in Booth 527.
Founded in 2004, EdXact SA focuses on electronic design tools aimed for physical verification tasks. EdXact’s innovative model order reduction technology helps accelerate extensive backend verifications in complex IC design cycles.