May 22, 2014 – Laguna Hills, CA – Excellicon Inc., an innovative provider of advanced Timing Constraints Analysis and Debugging solutions for the automation of timing constraints authoring, compiling, management, completion, and validation has announced several enhancements to its already strong portfolio of products. Excellicon will showcase the enhanced and new capabilities this year at Design Automation Conference in San Francisco.
Among the new capabilities is the FPGA support, which addresses the gap, which has always existed between FPGA and ASIC timing flows. Designers have always tried to manually manage the gap between the two methodologies and struggled to keep the timing requirements in sync on both FPGA and ASIC flows. Excellicon common database has the capability to manage the timing constraints for both methodologies in a single database and target the output to the appropriate flow.
Another enhanced capability in the tool is the timing constraints equivalence checking to manage the top-to-bottom or top-to-top equivalency. A formal based approach ensures that the lower level timing constraints is in-context to the top level constraints, or the top level constraints that was used for later phase of the design captures the same timing intent as the constraints used during an earlier phase. Designers now have the capability to make fast comparison of any number of constraints files at any layer of hierarchy.
Promotion and demotion of constraints files has always challenged the timing closure process. Traditional file based approach along with linting of constraints has left many gaps in the resulting constraints which needs to be covered manually. Using Excellicon products designer can easily promote the constraints from a lower layer of hierarchy to top level automatically, or vice versa; driving block level constraints from top level of hierarchy. Excellicon has expanded this capability with automatically deriving the constraints for the logic that is untouched by the promoted constraints. This fully automated capability significantly increases the resulting constraints accuracy and completeness as well as shortening the time required to generate the constraints by orders of magnitude.
Excellicon has also enhanced its formal timing exception generation and verification engine by introducing classification of timing intent related exceptions. These exceptions although not formal are often used by designers for the purpose of timing relaxation. Up until now there was no means of validating these exceptions. This new offering from Excellicon is the first in the industry, which helps the designer quantify and validate the correctness of this type of exceptions.
In addition to timing related issues Excellicon now can also provide an automated setup files for many leading Clock Domain Crossing tools, extending the timing impact of the design into functional space. Currently CDC tools are designed to work at a given layer of hierarchy and for a given mode. Even then the setup process is for the most part manual and iterative process, leaving the designer the task to figure out the clocking scheme and configuring the design for a given mode. Various tools claim hierarchical capability by utilizing black or gray boxing schemes applying towards various layers of hierarchy to improve capacity or noise, yet each time the designer needs to do the manual setup. The designers’ challenge in performing CDC analysis is to come up with proper setup file each time for each layer of hierarchy and each mode in order for the CDC tool to generate a usable and meaningful output. The setup requires a great deal of design knowledge with regards to clocking and control logic of the design. Some vendors also provide setup checks (lint) to prune the issues in setup files. Solving the complex setup process provides a unique advantage for designer and allows them to perform true hierarchical analysis as opposed to managing each layer of hierarchy manually. Excellicon automated approach allows user to produce setup files with complete clocking information and clock relations as well as correct mode settings in seconds while enabling a true hierarchical multi mode CDC analysis. Additionally the new versions of the tools are capable of analyzing CDC reports for impact of any timing exceptions on functional CDC paths and/or vice versa.
Through formal extraction of clocks, Excellicon provides a very comprehensive set of clock tree and clock domain analysis capability. Designers can very easily view clocks extracted either from actual RTL or SDC files and perform automated and manual analysis using the various visual aids in the tool. Products now have several additional features for design analysis that help designers in pruning common design issues such as snake paths inherent in hierarchical designs, or for analyzing the derating impact on clock trees. These features enable the designers to realize the impact and to take corrective actions early during the design cycle.
Merged mode constraints allow designers to speed up the timing closure process while considering collective impact of timing constraints on eventual timing of the chip. The challenge for designers is to manually generate merged mode constraints. Excellicon automated approach allows designers to generate as many modes as necessary in a couple of automated short steps and allow designers to generate merged mode constraints for any combination of constraints files. The products ensure accuracy and correctness of resulting merged mode constraints.
In the current geometries the SI is playing an important role and severely affects the timing window calculation. STA tools will report overly pessimistic results if the timing constraints are not coded for SI compliancy. Unfortunately, designers generally do not pay attention to SI effects when manually coding the timing constraints. Excellicon’s new capability eliminates this problem by incrementally adding required constraints to the original manually written timing constraints in order to enable SI compliancy.
“Excellicon ability to provide an end-to-end platform of complete timing constraints solution offers unique opportunities to designers not only to address the timing issues but also help them to close the gap between various stages of the design flow. Our goal is to minimize the amount of error prone manual work a designer has to perform in generating and validating the timing constraints, thus reducing the verification burden as well as eliminating the risk often involved in transferring data back and forth between various tools” said Rick Eram, VP of Sales and Marketing at Excellicon.
The designers can schedule private demos to check the unique capabilities of Excellicon products demonstrated at the upcoming Design Automation Conference this year in San Francisco at booth 2406.
Excellicon is an innovative provider of Timing Constraints Analysis and Debugging solutions for the automation of constraints authoring, completion, and validation from RTL to GDS with necessary analysis and debugging infrastructures. Excellicon products CONstraints MANager, CONstraints CERTifier, and CONSTAr address the needs of designers at every stage of SOC design and implementation in a unified environment. Timing Closure; Done Once! Done Right! Done FAST! www.excellicon.com