Don’t Miss Cadence’s In-Depth Tech Demos at DAC 2014



Cadence® technology experts will be out in full force at DAC 2014 in San Francisco, California. Don’t miss their in-depth presentations and demos of our technologies and methodologies for developing the highest quality silicon, SoCs, and complete systems at lower costs.

Reserve your spots today! Sessions will take place in our demo suites in booth 2610.

The table below provides a schedule and summaries of topics planned for our demo suites. Get more session details  here

Benefits of Mixed-Signal, OpenAccess, Interoperable Flow Learn how Cadence’s Virtuoso® and Encounter® Digital Implementation flow integrated on OpenAccess enables easier collaboration between analog and digital designers, resulting in fewer design iterations, shorter design cycles, and more predictable design closure. Suite 1:  Monday at 10:00am, Tuesday at 3:00pm
Advanced Mixed-Signal Verification Methodologies for ICs and SoCs Understand the advanced verification methodologies available to improve verification accuracy, performance, and productivity for complex mixed-signal IP, ICs, and SoCs. Suite 1:  Monday at 4:00pm, Wednesday at noon
Comprehensive Low-Power Solution – A Must for Today’s Complex Power-Managed Designs Learn about Cadence's comprehensive and production-proven low-power solution and advanced low-power techniques that help you get your power-managed designs done right and on time. Suite 1:  Tuesday at 4:00pm, Wednesday at 10:00am
System Interconnect Planning to Optimize Cross-Fabric Integration for Cost and Performance Learn how Cadence OrbitIO™ technology enhances cross-fabric planning and assessment by unifying silicon, package, and board data in a single canvas environment where assignment and connectivity scenarios are easily derived and evaluated in the context of the complete system. Suite 1:  Tuesday at 10:00am, Wednesday at 3:00pm
DDR4 Signoff:  Chip-Package-Board IO-SSO Analysis Find out how Cadence Sigrity™ IO-SSO Analysis Suite is used as a signoff methodology along with Cadence chip, package, and PCB implementation tools to ensure that DDR4 interfaces can be successfully implemented in spite of tight project schedules. Suite 1:  Monday at 2:00pm, Tuesday at 2:00pm
Full Custom and Analog Advanced Node Design See a live demo of Cadence Virtuoso® Advanced Node, a set of custom/analog capabilities for designing at 20nm and below. Learn about the solution’s many breakthrough custom/analog capabilities for advanced technology nodes. Suite 2:  Monday at 2:00pm, Tuesday at 10:00am
Electrically Aware Design: Addressing  the Productivity Gap in Analog Design Watch a demo on how electrically aware design (EAD) methodology can reduce design time by as much as 30% and allow you to take greater advantage of new advances in silicon technology. Find out how EAD will reduce complexity and uncertainty through electrical assessment, verification, and optimization of each incremental physical design decision. Suite 2:  Monday at noon, Tuesday at 3:00pm
Using Virtuoso Space-Based Router for Pin-to-Trunk Routing Cadence Virtuoso Space-Based Router is a connectivity-driven and constraints-driven router fully integrated into our Virtuoso Layout Suite. This session focuses on a productivity-enhancing feature of the product for pin-to-trunk routing. Suite 2:  Monday at 10:00am, Wednesday at noon
Spectre Simulation Technology - Addressing the Challenges of Advanced Node Design Cadence's Spectre® simulation technology enables scalable performance across all circuit types, integration into advanced solutions, and analysis features required for advanced nodes. See how Spectre technology addresses the increased performance requirements with new algorithms, verification automation at the transistor level, and visibility into the impact of variation on your design. Suite 2:  Tuesday at 2:00pm, Wednesday at 5:00pm
Characterization for Advanced Nodes Learn about Cadence’s characterization solution, which combines the industry-standard Virtuoso® Liberate and Spectre® solutions. The two solutions deliver the throughput needed for the increasing number of cells and PVT corners through Spectre SKI integration. Suite 2:  Monday at 11:00am, Wednesday at 2:00pm
Metric-Driven Verification from IP to SoC with Incisive vManager Solution Gain insights into Cadence’s Incisive® vManager™ planning and management solution, which supports multiple simultaneous users across multiple specialized verification engines, as well as pipelined projects with real-time collaboration, coordination, and control over the verification process. Suite 2:  Tuesday at 4:00pm, Wednesday at 10:00am
SimVision and Incisive Debug Analyzer Reduce Debug Time from Days to Minutes Get an overview of Incisive Debug Analyzer, and watch a demo showing how, using SimVision, you can significantly improve debug productivity with object-oriented, class-based, coverage-driven verification environments like those built with the Universal Verification Methodology (UVM). Suite 2:  Monday at 4:00pm, Tuesday at noon
Incisive Verification Apps: Automated Formal Solutions for Common Verification Issues See how Incisive verification apps bring together optimal combinations of formal and dynamic verification technologies to solve some of the biggest verification problems. Suite 2:  Monday at 3:00pm, Tuesday at 11:00am
High-Level Synthesis Improves Time to Market, Quality of Results, and IP Reuse Design and verification engineers worldwide have used Cadence’s high-level synthesis (HLS) solutions to produce silicon in products found in your home, office, and pocket. See how HLS is being used to achieve 10X more productivity, 5X faster verification speed and better effectiveness, and 20% better Quality of Results in terms of area, performance, and power. Suite 2:  Monday at 1:00pm, Wednesday at 3:00pm
What's New with the Palladium XP Series Learn about new productivity enhancements in Cadence Palladium® XP series that will accelerate your system-level bringup, validate your designs with industry-standard low-power verification techniques, virtualize your debug efforts, and expand your coverage analysis from IP to SoC. Suite 2:  Tuesday at 5:00pm, Wednesday at 1:00pm
Accelerating Embedded Software Development with Cadence Rapid Prototyping Platform Watch this demo for an overview of hardware/software development techniques including advanced hardware/software debug, as well as FPGA-based prototyping as a proven and widely used methodology for early software development. Learn how to implement a complete SoC design with embedded processor, embedded graphics core, and various interfaces on the Cadence Rapid Prototyping Platform (RPP). Suite 2:  Monday at 5:00pm, Wednesday at 4:00pm
ARM v7 and v8 Based Accelerated System Development See a comprehensive flow on how to optimize and accelerate hardware and software development for ARM®-based systems. The overview will cover ARMv8 64-bit and v7 32-bit Cortex® based embedded software development with the Palladium Hybrid solution. Suite 2:  Tuesday at 1:00pm, Wednesday at 11:00am
RTL Design in a Physical World: Synthesis and Test Learn how physical modeling requirements are changing the synthesis paradigm at the lower geometries where wires dominate. This physical scope can be used to impact the way gates are structured and mapped to more accurately predict the timing and area after real wires are routed as leveraged in the Encounter RTL Compiler Advanced Physical Option. Suite 1:  Monday at 1:00pm, Tuesday at 5:00 pm
Tackling the Most Difficult ECOs with ‘Congestion and Timing Smarts’ Learn how you can leverage Encounter Conformal ECO Designer to drastically reduce your ECO cycle time with fewer resources.  Find out how Tempus™ Timing Signoff Solution can complete the final steps to be timing-clean with massive parallelization, accuracy, and integration with Encounter Digital Implementation System. Suite 1:  Monday at noon, Wednesday at 11:00am
High-Performance, Advanced-Node Encounter Digital Implementation Learn about the First Encounter® Design Exploration and Prototyping solution for optimized floorplans and the Encounter Digital Implementation System GigaOpt route-driven optimization and CCOpt clock-concurrent design to get a head start on your flow development. Suite 1:  Tuesday at noon, Wednesday at 2:00pm
Scalable Timing and Power Signoff Analysis with Tempus and Voltus Solutions Learn how Cadence has achieved new limits in flat-level analysis capacity and runtime with Tempus™ Timing Signoff Solution and Voltus™ IC Power Integrity Solution, both of which feature massively parallel architectures. Suite 1:  Monday at 3:00pm, Tuesday at 11:00am, Wednesday at 1:00pm
Fast and Accurate Signoff Extraction for Advanced Nodes Come and hear about the latest advances in parasitic extraction technology. See how Cadence is addressing the challenges posed by advanced process nodes before they become a problem for you. Suite 1:  Monday at 11:00am
Foundry Qualified, Comprehensive Physical Signoff (Physical Verification and DFM) and Optimization for All Nodes Come and hear how Cadence has addressed physical signoff not only at final tapeout stage but also during the design implementation phase via with tight integration in our Virtuoso and Encounter platforms. Suite 1:  Tuesday at 1:00pm, Wednesday at 4:00pm

© 2014 Cadence Design Systems, Inc. All rights reserved. Cadence respects your online time and privacy.
Cadence Design Systems, Inc. | 2655 Seely Avenue San Jose, CA 95134

Review Article Be the first to review this article
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy