AMIQ EDA Offers Enhanced UVM Support in the DVT Eclipse IDE
| | Rate | Review | Notices

April 30, 2014 -- In March, this year, AMIQ EDA announced version 3.5 of its flagship solution – DVT Eclipse IDE. The new version provides enhanced compilation, improved UVM support, a streamlined GUI, and simplified deployment to help design and verification engineers increase code development quality and productivity.

The DVT IDE is a complete and powerful code development environment for the design and verification languages e, SystemVerilog, Verilog, VHDL, built on the Eclipse Platform.  It helps engineers overcome the limitations of plain text editors and benefit from the advanced features of a totally integrated code development solution that works across languages, enabling them to:

  • Increase the speed and quality of new code development
  • Simplify the maintenance of legacy code and reusable libraries
  • Manage effectively multi-language projects
  • Accelerate language and methodology learning
  • Build UVM-compliant verification environments
  • Cope easier with the increase in design complexity

Some of the major capabilities that DVT version 3.5 introduced to its users are in connection to providing enhanced UVM Support. The newly added capabilities help simplify browsing the structure of an UVM-based verification environment and include:

  • UVM Browser View that helps explore the UVM classes grouped by categories such as agents, drivers, and sequences as well as easily inspect the UVM flow-specific API like overridden phases and fields registered to the factory.
  • Verification Hierarchy View, which lets the user see the top-down topology of a UVM verification environment based on UVM factory "create" calls.
  • UVM Factory Queries for "config db setters", "config db getters", and "factory overrides" that help quickly and accurately locate UVM factory-related constructs that may influence the behavior of a testbench.

DVT provides an extended set of UVM-oriented features. Below are some of the previously existing features that our customers have appreciated:

  • Code Templates – parameterized code snippets that help write code faster while maintaining consistency throughout the source code.
  • Project Templates – parameterized directory trees and source code content that enable users follow the recommended UVM layout throughout verification projects.
  • Architecture Diagrams – dynamically created UML diagrams that show the relationships between all user-defined UVM-based classes and help inspect and document the verification environment architecture.
  • Sequence Diagrams – allow users to visualize all the UVM-based sequences and how they relate to one another. This capability simplifies understanding the stimuli generation capabilities of the verification environment.
  • Log Analysis and Back Annotations to the Source Code ­– offers a smart way to visualize and browse a simulator's output on the DVT console. The errors and warnings in the simulation log are hyperlinked with the source code, so that the user can jump directly where the problem is. The log content is also color-coded based on the message source and severity.
  • UVM Field Editor – simplifies field registration, a process that is usually tedious and time consuming. It also enables users to quickly check whether they have unregistered fields or registration errors.
  • Override Functions – helps quickly override functions or tasks inherited from UVM base classes. It automatically inserts the proper function declaration code (all proper arguments, implicit super call). It also adds a TODO reminder to fill in the code.
  • Macro Expansion – allows users to investigate the errors inside a macro by letting them examine and debug macro code fragments in context with the source code.
  • In-line Documentation – lets users access information about any UVM entity in a tooltip. There is no need to open additional user guides or reference documentation.
  • UVM Content Filters – eliminate the unnecessary content overhead by automatically filtering out the irrelevant information from the UVM library.

In addition, DVT offers an innovative linting framework that allows engineers to automate the process of checking VIP against the UVM Compliance Checklist. It lets users effortlessly and consistently apply the UVM rules and ensure compliance to the official UVM methodology.

AMIQ will be exhibiting at DAC on June 2-4, 2014, in San Francisco, Booth # 1214. Stop by and see a demo of the DVT IDE. For more information, visit



Review Article Be the first to review this article

Featured Video
Principle Electronic Design Engr for Cypress Semiconductor at San Jose, California
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Director, Business Development for Kongsberg Geospatial at remote from home, Any State in the USA
Director, Business Development for Kongsberg Geospatial at Ottawa, Canada
Upcoming Events
IPC Technical Education - PCB Layout - Place and Route at Del Mar Fairgrounds 2260 Jimmy Durante Blvd. Del Mar CA - May 2, 2018
IPC Technical Education at Wisconsin Center 400 W Wisconsin Ave. Milwaukee WI - May 8, 2018
IPC High Reliability Forum at Embassy Suites: Baltimore-At BWI Airport 1300 Concourse Drive Linthicum MD - May 15 - 17, 2018
TrueCircuits: IoTPLL

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise