Technical Sessions and Demonstrations
June 2-4, 2014 from 9:00am-6:00pm at Booth #1521
Quick Intro to SCE-MI
OSVVM: Advanced Verification for VHDL with Synthworks
SoC Emulation Made Easy
Visual Mapping: GPS for UVM Journey
High Level Synthesis with NEC
Design Rule Checks in FPGA design
Prototyping over 100M Gates
Ask Aldec: Demos, Roadmaps, Partners, Q&A, etc.
1-on-1 Sessions fill up quickly.
to register. Choose one or more sessions and schedule a time that is convenient for you.
Aldec, Inc., headquartered in Henderson, Nevada, is a global industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions.