Excellicon's Automated CDC Setup Improves Noise in CDC Analysis and Provides Significant Productivity Advantage

March 25, 2014 - Laguna Hills, CA -- Excellicon Inc. an innovative provider of end-to-end timing constraints products announced release of automated CDC-Environment setup suite and CDC report analyzers to enhance and extend performance of any existing functional CDC tools. The users of Excellicon products can now very simply and automatically generate necessary seed setup environment files necessary for running their existing CDC tools based on advanced formal analysis. Excellicon generated CDC setup environment provides necessary files for any layer of hierarchy and for any mode of the design, enabling faster and accurate setup process. As a result of proper setup the resulting CDC reports will be more accurate and contain much less noise. In addition the user now has the option to close the loop between functional and timing domains and back annotate CDC results into timing constraints for noise-less analysis. 

“Performing CDC analysis today is a very time consuming, taking weeks of designers time. The manual setup process is usually error prone and done for one mode; functional mode, and a given level of hierarchy chosen to minimize analysis effort.  Despite such time consuming effort the setup environment is often incomplete, while the choice of hierarchy is generally dictated by tool capacity, leading to noisy reports and frustrated designers. Clock Domain Crossing products in the market place are fully dependent on user feedback and knowledge of spec as well as any available design information, which are then manually translated into a setup environment file for a single mode and for a given layer of hierarchy. As a result a comprehensive and full multi-mode hierarchical CDC analysis is often not a viable option due to high cost of setup for any design team.” said Rick Eram, VP of sales and marketing at Excellicon. 

He also added “Available CDC products are generally noisy and provide either a noise reduction scheme through tedious and manual setup process or later through elaborate and multi layer filtering/waiving of unwanted messages without proper propagation of such filtering to next layer of hierarchy. All the effort is to compensate for incomplete setup and lack of propagation of accurate setup information through out the design layers. Excellicon can eliminate much of guess work form the process while offering accuracy of automation in seconds.“ 

It is also important to note that Excellicon’s approach depends on actual design as opposed to legacy timing constraints. Use of legacy timing constraints files as a seed input for CDC setup where there’s often issues left from older versions of the timing constraints leads to inaccurate setup, and added noise. Also complicating matters is lack of availability of the timing constraint files, which are traditionally developed by implementation engineers and therefore invariably not available when the RTL is being coded and analyzed for CDC issues.

Through this offering Excellicon provides significant productivity gain by automation of CDC setup process and providing capability to back annotation CDC results into timing constraints files. User can now minimize manual duplication of CDC setup effort while enabled to perform in-depth hierarchical analysis with much less noise. Empowering designer to choose hierarchy level allows designer to improve CDC tool performance and manage the capacity related issues with ease.

About Excellicon
Excellicon is an innovative provider of end-to-end Timing Constraints Analysis and Debugging solutions for the automation of constraints authoring, completion, and validation from RTL to GDS with innovative analysis and debugging infrastructures. Excellicon products CONstraints MANager, CONstraints CERTifier, and CONSTAr address the needs of designers at every stage of SOC design and implementation in a unified environment. – Timing Closure; Done Once! Done Right!

For further information contact:
Fia Johansson


Read the complete story ...

Review Article Be the first to review this article

Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
H-1B Visa: de Geus’ tragedy looms large
Peggy AycinenaIP Showcase
by Peggy Aycinena
IP for Cars: Lawsuits are like Sandstorms
More Editorial  
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
Staff Software Engineer - (170059) for brocade at San Jose, CA
Technical Support Engineer for EDA Careers at Freemont, CA
ASIC/FPGA Design Engineer for Palo Alto Networks at Santa Clara, CA
Mechanical Designer/Engineer for Palo Alto Networks at Santa Clara, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Upcoming Events
2017 IoT Developers Conference at Santa Clara Convention Center California - Apr 26 - 27, 2017
Embedded Systems Conference ESC Boston 2017 at Boston Convention & Exhibition Center Boston MA - May 3 - 4, 2017
2017 GPU Tech Conference at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - May 8 - 11, 2017
High Speed Digital Design and PCB Layout at 13727 460 Ct SE North Bend WA - May 9 - 11, 2017
Verific: SystemVerilog & VHDL Parsers

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy