DVCon 2014 Announces Strong Numbers, Best Oral Presentation & Best Poster Awards

Continues to see growth in attendance, especially for technical content

Louisville, CO – March 7, 2014 –The Design and Verification Conference (DVCon), sponsored by Accellera Systems Initiative, concluded this week with strong numbers in attendance, number of poster sessions, number of tutorials, number of papers submitted and number of exhibitors.  

Overall attendance, including exhibit-only and technical conference attendees was 879.  Attendance was further enhanced by more than 294 exhibitor personnel that also had access to the panels and keynote, for a total of 1,173 participants.  The conference attracted 41 exhibitors, including 15 first timers and 10 international. 

The Award for Best Oral Presentation, as voted by conference attendees, went to Kelly D. Larson, NVIDIA Corp. for his presentation titled, “Determining Test Quality through Dynamic Runtime Monitoring of SystemVerilog Assertions.”  Two Honorable Mentions were awarded:  “Sign-off With Bounded Formal Verification Proofs,” by Vigyan Singhal and HarGovind Singh, Oski Technology, Inc.; and NamDo Kim and Junhyuk Park, Samsung Electronics Co., Ltd; and “Digitizing Mixed Signal Verification: Digital Verification Techniques Applied to Mixed Signal and Analog Blocks and System Level Verification,” by David C. Brownell and Courtney Schmitt, Analog Devices, Inc.

Best Poster Presentations were awarded for the second year.  Top honors went to Rich Edelman and Raghu Ardeishar, Mentor Graphics for their poster, “UVM SchmooVM – I Want My C Tests!” Two Honorable Mentions were also awarded:  “Supercharge Your Verification Using Rapid Expression Coverage as the Basis of a MC/DC-Compliant Coverage Methodology,” by Gaurav K. Verma and Doug Warmke, Mentor Graphics Corp. and “The Future of Formal Model Checking is NOW! Leveraging Formal Methods for RAPID System on Chip Verification,” by Ram Narayan, Oracle Labs.

“We are very proud of the turnout and program presented at DVCon this year,” stated Stan Krolikoski, Ph.D., DVCon General Chair and Distinguished Engineer at Cadence.  “We sought to expand the conference focus from solely being on ‘design and verification’ to also include hot topic areas that are critical to our attendees.  We made a concerted effort to provide attendees with real solutions to the problems they are facing today, and I believe many left the conference with newly applicable knowledge.”

“The trend toward excellence continued this year as The Technical Program Committee was pleased to receive another record number of high quality, valuable submissions,” commented Ambar Sarkar, Ph.D., DVCon Program Chair and Chief Verification Technologist at Paradigm Works.  “It is evident in the attendance we see for the papers, tutorials and posters that the content continues to be of great interest.  Because we consistently receive more submissions than we can accept, the bar is quite high for quality content and our presenters didn’t disappoint.”

Highlights of the Week:

The keynote address, “An Executive View of Trends and Technologies in Electronics,” presented on Tuesday by Lip-Bu Tan, president and CEO of Cadence Design Systems, drew a standing room only crowd.  He discussed some of the many challenges faced by the EDA industry and how new design technologies are essential for continued innovation.

The panel, “Did We Create the Verification Gap?” moderated by John Blyler, chief content officer, Extension Media was well attended and raised a number of questions from the crowd. Some asked if it might be beneficial for designers to feel more of the pain that verification engineers are faced with.

Accellera Systems Initiative Day kicked off the conference on Monday.  Andrew Goodrich was recognized during the Accellera-sponsored luncheon as the recipient of the third annual Accellera Technical Excellence Award.  He is a member of the SystemC Language Working Group (LWG).

The DVCon Steering Committee values all feedback regarding the conference.  Attendees have been given a survey and are asked to provide input on how to make DVCon 2015 even better.

Save the date:  DVCon 2015 will be held March 2-5, 2015.

About DVCon

DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an industry consortium dedicated to the development and standardization of design and verification languages. For more information about Accellera, please visit www.accellera.org. For more information about DVCon, please visit www.dvcon.org.



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