Wasga Compiler Demo and Tutorial for Predictable FPGA Based Prototyping at Booth #904
WHO: Flexras Technologies, the provider of high performance partitioning design suite tools for FPGA-based prototyping
WHAT: Flexras will demonstrate Wasga Compiler and showcase its user-friendly hybrid RTL/Gate partitioning approach for predictable FPGA-based prototyping at the Design and Verification Conference (DVCon 2014)
Zied Marrakchi, Flexras CTO, will present a tutorial entitled “ The best of both worlds: Timing driven hybrid RTL/Gate partitioning for predictable FPGA based prototyping” at booth #904
Traditional prototyping solutions manage DUT partitioning either in RTL or in gate level and fail to propose predictable and efficient flow allowing to quickly bring-up FPGA based SoC prototype. This tutorial shows FPGA-based prototyping challenges and presents an innovative methodology unifying the benefits of both gate-level partitioning and RTL partitioning, providing error free implementation and predictable short time-to-prototype.
Monday, March 3, from 5 p.m. until 7 p.m.,
Tuesday and Wednesday, March 4-5, from 2:30 p.m. until 6 p.m.
WHERE: Booth #904, Doubletree Hotel in San Jose, Calif.–
For More Information
For more information about Flexras, please visit http://www.flexras.com
To set an appointment with Flexras, please contact Hayder Mrabet at Email Contact
About DVCon: www.dvcon.org.
Flexras Technologies develops and commercializes EDA partitioning tools for the FPGA and SoC markets. Flexras patented and proven timing-driven partitioning technology are used by world leading semiconductor manufacturers, and licensed to FPGA-based emulator provider. Flexras addresses growing SoCs development complexity and risks by accelerating cost effective rapid prototyping targeting multi-FPGA-based systems. Flexras Technologies is headquartered in Paris Saint-Denis France. For more information, please visit
l’Ops PR- Paris, France
: +33(0)622 980 380+33(0)622 980 380