Digital Core Design, IP Core provider and a System-on-Chip design labs from Poland, introduced its latest solution, the DSMART. Based on ISO 7816-3/EMV4.2 requirements, it implements the hardware support for both T0 character oriented protocol and T1 block oriented protocol. Ipso facto, the Core is an answer to growing demand for solutions supporting the IC chip systems, visible in the previous months.
Bytom-Poland, January9th, 2014 -- The DSMART is a fast, versatile and cost-competitive IP Core intended for smart card reader applications. It’s been designed to combine highly reduced CPU utilization & low area consumption, and to be able to activate and deactivate cards, perform resets, handle ATR reception and many additional features. - Small size, mobility and easy interaction with computers or other automated systems, createan instant demand for smart card systems – says Jacek Hanke, DCD’s CEO - Immediate update of the stored data opens new markets for the smart card systems e.g. in healthcare (identification and patient authentication), banking (wireless payment), transportation (electronic ticketing) and many others.
The DSMART is a configurable IP Core, so it can be easily adjusted to the project’s needs. Among proprietary options one can find, there’s e.g. data transfer to and from the host system which can be interrupt-driven or executed through Direct Memory Access (DMA). The automatic convention detection and decoding mechanism ensure the exact result, no matter of the used convention. Elementary Time Unit (ETU) - time duration of one bit is decoded from the received ATR interface byte and generated automatically. The card clock divider provides non-gated clock with a wide range of possible frequencies.
DSMART IP Core implements also a special power down mode, in which the card clock is being hold in two possible states, depending on the card parameter. Error signaling and character repetition are automatic for the T0 protocol. The DSMART incorporates also an optional CRC/LRC hardware checking and generation mechanism which gives the convention independent result. The received CRC/LRC is not stored in the FIFO, so it can be read in case of CRC/LRC error. And, last but not least, the newest DCD’s IP Core provides optional block length counter to secure the DMA block transfer and automatic CRC/LRC, subjoining with a manual affixing option.
More information: http://dcd.pl/ipcore/884/dsmart/
- Compatible with the ISO 7816-3: 2006 and EMV 4.1 standard
- Support for asynchronous Smart Cards
- Dual configurable length FIFO with two programmable thresholds
- Card detection input
- Software-configurable interrupts
- Automatic convention detection and decoding
- Programmable non-gated card clock generator
- Automatic ETU generator
- DMA support for transmit and receive
- Hardware CRC and LRC calculations
- Card power down mode with clock stop high and clock stop low possibility
- Special fast block mode for T1 protocol (optional)
- CRC/LRC hardware generation and checking
- Byte counter with automatic CRC/LRC affixing(optional)
- No inertial tri-state buffers
- Fully synchronous synthesizable design
Information about Digital Core Design:
In 2014 Digital Core Design celebrates its 15th Anniversary. The company founded in 1999, since the beginning stands in the forefront of the IP Core market. High specialization and profound customer service enabled to introduce more than 70 different architectures. Among them is the world’s fastest 8051 IP Core, the DQ80251, which is more than 66 times faster than the standard solution. As an effect, over 300 hundred licensees have been sold to more than 500 companies worldwide. Among them are the biggest enterprises like e.g. Sony, Siemens, General Electric and Toyota. But a lot of DCD’s customers are small businesses, R&D laboratories or front/back end offices, which require exact solution tailored to their project needs. Rough estimations say that more than 250 000 000 devices around the globe have been based on Digital Core Design’s IP Cores.
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